JPS59220970A - Gto of amplifying gate structure - Google Patents

Gto of amplifying gate structure

Info

Publication number
JPS59220970A
JPS59220970A JP9744483A JP9744483A JPS59220970A JP S59220970 A JPS59220970 A JP S59220970A JP 9744483 A JP9744483 A JP 9744483A JP 9744483 A JP9744483 A JP 9744483A JP S59220970 A JPS59220970 A JP S59220970A
Authority
JP
Japan
Prior art keywords
layer
gate
gto
current
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9744483A
Other languages
Japanese (ja)
Inventor
Satoshi Ishibashi
石橋 聰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Corp, Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Corp
Priority to JP9744483A priority Critical patent/JPS59220970A/en
Publication of JPS59220970A publication Critical patent/JPS59220970A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/74Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744Gate-turn-off devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To reduce the gate impedance by a method wherein two N type regions are provided in the surface P layer of a semiconductor substrate of P-N-P three-layer structure, and then the auxiliary and main GTO's are constructed while including those, respectively, a split resistor in parallel with the surface is provided in the N type region, the gate current at the time of turn-on is passed through this resistor, and is not passed at the time of turn-OFF. CONSTITUTION:Using the semiconductor substrate of P0N1P1 three-layer structure, the N type regions N2 and N3 are diffusion-formed in the P0 base layer of the uppermost layer, and the substrate side including the region N2 is used as the auxiliary GTO, and that including the region N3 as the main GTO. A gate electrode G1 for on-current supply is provided outside the region N2 by being positioned above the P0 layer, an auxiliary gate electrode GA outside the region N3, and further a gate electrode G2 for off-current lead-out between the regions N2 and N3. In this construction, P1<+>, P0<+>, and P2<+> layers are buried in the P0 layer while being made parallel with the surface, and the arcing current is controlled by means of lateral resistors Rg1 and Rg2 generated therebetween.

Description

【発明の詳細な説明】 本発明は増幅ゲート構造のゲートターンオフサイリスタ
に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate turn-off thyristor with an amplifying gate structure.

ゲートターンオフサイリスク(以下GTOと称す)け一
般に点!IJIffl流が通常のサイリスタに比較して
大きいため、ゲート回路が大型になる欠点がある。この
欠点を改善するために、近年増幅ゲート構造を有するG
TOが開発されtoこの増幅ゲート構造()Toの動作
は普通のサイリスタと変わりないが、補助サイリスタと
称される部分もGTO構造になっていることに%徴があ
−る。第1図はゲートドライブ回路を有する増幅ゲート
構造a’rOの構成説明図であり、この第1図のGTO
は埋込ゲート構造の例である。第1図に訃いて、()T
Gate Turn Off Sailisk (hereinafter referred to as GTO) is generally a point! Since the IJIffl flow is larger than that of a normal thyristor, there is a drawback that the gate circuit becomes large. In order to improve this drawback, in recent years G
Since the TO has been developed, the operation of the amplification gate structure (TO) is no different from that of an ordinary thyristor, but the feature is that the portion called the auxiliary thyristor is also a GTO structure. FIG. 1 is an explanatory diagram of the configuration of an amplification gate structure a'rO having a gate drive circuit, and the GTO in FIG.
is an example of a buried gate structure. As shown in Figure 1, ()T
.

/けpt NIPN、層から成る補助GTOであり、G
TOJけPi NI PN、層から成る主()Toであ
る。
/ketpt NIPN, is an auxiliary GTO consisting of layers, and G
TOJ ke Pi NI PN, is the main ()To consisting of layers.

前記GTO/とGTo、2のPベース層中には高濃度不
純物@PL+とP2+とが埋込み形成されている。
High concentration impurities @PL+ and P2+ are embedded in the P base layers of GTO/ and GTo,2.

RけPベース層の横方向抵抗を示す。このように構成さ
れたGTO全ターンオンさせるにはグー巳 ト制御電源回路Jのスイッチ4taをオンさせて直流電
源!。から外部ゲート端子ao→、ゲート電極G、→抵
抗Rg−+N2謡→埋込みp 、+層→N3層→カソー
ドに→スイッチ4ta→直湾電源5aのループを通して
オンゲート電流を流し、こルによってまず補助GTOを
ターンオンさせる。この時流詐る主電流が増幅ゲート電
済としてN!層から補助ゲート電極GA→埋込みP2+
層→N3層→カソードに→負荷インピーダンスt→直流
電源7→アノードAへと流れ、これによって主GTOが
ターンオンする。一方、このGTOをターンオフさせる
にはゲート制御用電源回路Jのスイッチvaをオフさせ
るとともにスイッチケ1)をオンさせて直流電源5bか
らスイッチ≠b→カソードK −+ N 3層→埋込み
P 1+ffi→ゲート電極G2→ツエナーダイオード
ざ→ダイオード9→外部ゲート端子G。
R and P show the lateral resistance of the base layer. To turn on all of the GTO configured in this way, turn on the switch 4ta of the control power supply circuit J and turn on the DC power! . From the external gate terminal ao →, gate electrode G, → resistor Rg - + N2 line → buried p, + layer → N3 layer → cathode → switch 4ta → direct current is passed through the loop of power supply 5a, and this first auxiliary Turn on the GTO. This current flow main current is N! From layer to auxiliary gate electrode GA → buried P2+
It flows from the layer to the N3 layer to the cathode to the load impedance t to the DC power source 7 to the anode A, thereby turning on the main GTO. On the other hand, to turn off this GTO, turn off the switch va of the gate control power supply circuit J and turn on switch 1). Electrode G2 → Zener diode Z → Diode 9 → External gate terminal G.

→直流電源、tbのループを通してオフゲート電流を流
し、こnによって主()T O’5ターンオフさせる。
→The off-gate current is passed through the loop of the DC power supply and tb, and this turns off the main ()TO'5.

この時ツェナーダイオ−トイおよびダイオード?で生ず
る電圧降下分が叩込みP?+層および補助ゲート電極G
Aを介してN2層とゲート電極G1の間に逆バイアス電
圧として印加されるので、補助GTOに涼れる電流の一
部は抵抗B、全全通てゲート電@GI仙(へ引き出され
、これによって補助GTOもターンオフさnる。
Zener diode and diode at this time? Is the voltage drop caused by the impact P? + layer and auxiliary gate electrode G
Since it is applied as a reverse bias voltage between the N2 layer and the gate electrode G1 through A, a part of the current flowing to the auxiliary GTO is drawn out to the resistor B, and the entire gate voltage is drawn out to the gate electrode G1. The auxiliary GTO is also turned off.

上記のような+7TOのターンオンおよびターンオフ時
の動作は次のような問題点があった。すなわち主GTO
のターンオフ時の電流はツェナーダイオードgおよびダ
イオード?金流れるので、こルらの電圧時“下によって
オフドライブ回路の電力損失が増大することである。ま
た、ターンオフ時に補助GTOをinるTL淀は抵抗R
5,全通ってゲート電極G、側、へ引き出されるが、こ
の抵抗R9の値を小さくすnばするほど前記オフゲート
電流の引き出しが容易になってGTOのゲート遮断能力
は向上する。しかし反面、抵抗R9の値を小さくすると
GTOのターンオン時の定格臨界オン電1 流上昇ホ、すなわち一耐憬が著しく低下してしt まり問題がある。
The turn-on and turn-off operations of the +7TO as described above have the following problems. i.e. the main G.T.O.
What is the current at turn-off of Zener diode g and diode? Since gold flows, the power loss of the off-drive circuit increases due to the voltage drop below these voltages.Also, the TL stagnation that connects the auxiliary GTO at turn-off is connected to the resistor R.
5. All of the current is drawn out to the gate electrode G side, but the smaller the value of this resistor R9, the easier it is to draw out the off-gate current, and the gate cutoff ability of the GTO is improved. However, on the other hand, if the value of the resistor R9 is made small, there is a problem in that the rated critical on-current rise when the GTO is turned on, that is, the resistance to cold, decreases significantly.

本発明は上記の点に鑑みなさf′L念もので、()TO
のゲート遮断能力t tftなうこと無くターンオン時
1 のatilii+量および点弧特性を向ヒさせるととも
に、GTOのオフドライブ回路の電力損失を低減するこ
とができる増幅ゲート構造のGTOを提供することを目
的としている。
In view of the above points, the present invention has been made in consideration of the above points.
It is an object of the present invention to provide a GTO with an amplified gate structure that can improve the gate cut-off capability ttft at turn-on and the ignition characteristics without decreasing the gate cut-off ability ttft, and reduce the power loss of the off-drive circuit of the GTO. The purpose is

以下図面を参照しながら本発明の一実施例を説明する。An embodiment of the present invention will be described below with reference to the drawings.

第2図において第1r21と同一部分は同一符号を持っ
て示し、その説明は省略する。GTO/はP菫NI’p
o N1層から成る補助GTOであり、()To、2は
Pt N+ Pn Ns F’Jから成る主()Toで
ある。N2pPaとN3層を挾む位(りのPoベース層
表面にはオフ電腑引へ出し用ゲート電極G2が設けられ
ている。Nz層の前記ゲート電極G2に対して反対側々
なる位置CGTOの中央部)のPoベース層表面にはオ
ン電流供給用ゲート′7I!極CcIが設けられている
。N3層表面VCけカソード電極Kが設けら几ている0
前記オン電流供給用ゲート電極G1に対して同心円上で
あるとともに前記カソード電極力)ら所定距離隔て念外
周のP。層表面には補助ゲート電@GAが設けられてい
る。この補助ゲート電@GAはN2層表面に設けた電極
と接続さnている。Paベース層はPベース円とそのP
ベース層中に埋込み形成さfLt高禍度不純物署p +
 (後述するPl” * ”O” * P2+)とでセ
フ成さnている。すなわちN2層の投影領域に位置する
Pベース層中には高濃変不純物層Pl+が故射状又は櫛
目状に埋込み形成され、またN3層の投影領域に位置す
るPベース層中には高0度不純物層p 、+が埋込み形
成され、さらにこnらPl+とF2+’iC結ぶ位置と
もに外部はP2+層と連結さfl−1:いる。RR1お
よびFq2は前記PI+’FJ I Po”M91 F
2+層から成る埋込みゲートの端部におけるPベース円
の横方向抵抗を示す。図中、K(1N3層の表面に設け
られ念力ソード電極であシ、Aはアノード′71I極で
ある。
In FIG. 2, the same parts as 1r21 are shown with the same reference numerals, and the explanation thereof will be omitted. GTO/HaP SumireNI'p
o It is an auxiliary GTO consisting of N1 layers, and ()To, 2 is a main ()To consisting of Pt N+ Pn Ns F'J. A gate electrode G2 is provided on the surface of the Po base layer to sandwich the N2pPa and N3 layers.A gate electrode G2 for leading out the off-electrode is provided on the surface of the Po base layer, sandwiching the N2pPa and N3 layers. On the surface of the Po base layer (in the center) is a gate '7I! for supplying on-current. A pole CcI is provided. A cathode electrode K is provided on the surface of the N3 layer.
P on the outer periphery, which is concentric with the on-current supplying gate electrode G1 and spaced a predetermined distance from the cathode electrode. An auxiliary gate electrode @GA is provided on the layer surface. This auxiliary gate electrode @GA is connected to an electrode provided on the surface of the N2 layer. The Pa base layer is the P base circle and its P
Embedded in the base layer fLt high-grade impurity sign p +
(Pl" * "O" * P2+, which will be described later). That is, in the P base layer located in the projection area of the N2 layer, a highly concentrated impurity layer Pl+ is formed in a radial or comb-like shape. A high 0 degree impurity layer p,+ is embedded in the P base layer located in the projection area of the N3 layer, and furthermore, both of the positions connecting Pl+ and F2+'iC are connected to the P2+ layer on the outside. fl-1: Yes. RR1 and Fq2 are the same as the above PI+'FJ I Po"M91 F
Figure 2 shows the lateral resistance of a P base circle at the end of a buried gate consisting of a 2+ layer. In the figure, K is the telekinetic sword electrode provided on the surface of the 1N3 layer, and A is the anode '71I pole.

このように構成さn?c G T Oにおいてゲートド
ライブ回路は次のように接続さ扛ている。すなわち、オ
ン電流供給用ゲート電極G、に接続さnた外部ゲート端
子Goとカソード電極にの間にはゲート制御用電源回路
Jが接続され、前記Pl極G1とオフ電流引き出し用ゲ
ート電極G2の間には図示極性のダイオード9が接続さ
れている。
Is it configured like this? In the cGTO, the gate drive circuit is connected as follows. That is, a gate control power supply circuit J is connected between the external gate terminal Go connected to the on-current supply gate electrode G and the cathode electrode, and the gate control power supply circuit J is connected between the Pl pole G1 and the off-current extraction gate electrode G2. A diode 9 of the illustrated polarity is connected between them.

上記のように構成されたGTOf:ターンオンさせるに
はゲート制衛1用電源回路JのスイッチUaをオン点せ
て直情電源jahら外部ゲート端子G0→ゲート電極G
1 →1氏抗B61−+N2 層→補lカグート電極G
A→抵抗R,72→N3M→カンード電極に→スイッチ
ga→直流織源5aのループを通してオンゲート電流′
fCiし、これによってまず補助GTOをターンオンさ
せる。この時碓れる電流が増幅ゲート電流としてN2層
から噛助グート電極G4→抵抗R2→N3層→カソード
@WLK→負荷インピーダンスt−+直鯖電源ン→アノ
ード′鷹極Aへと流れ、こnによって主GT(M’lf
カーフオンする0コノヨウに補助()TOのターンオン
電離は抵抗Rqtを通過し、主GT(lのクーンオン電
漆は抵抗′E3が全通過中るので、小さな点弧電流で補
助()TOおよび主GTO全点弧することができて点弧
特性が高めら力、る。
GTOf configured as above: To turn on, switch Ua of power supply circuit J for gate control 1 is turned on, direct power supply jah, external gate terminal G0 → gate electrode G
1 → 1st anti-B61-+N2 layer → Complementary Kagut electrode G
A → Resistor R, 72 → N3M → Cando electrode → Switch ga → On-gate current ' through the loop of DC source 5a
fCi, thereby first turning on the auxiliary GTO. The current flowing at this time flows as an amplification gate current from the N2 layer to the support gate electrode G4 → resistor R2 → N3 layer → cathode @WLK → load impedance t- + direct power supply → anode 'hawk electrode A, and so on. The main GT(M'lf
The turn-on ionization of the auxiliary ()TO passes through the resistor Rqt, and the turn-on ionization of the auxiliary ()TO passes through the resistor Rqt, and the main GT (l) has a resistor 'E3 passing through it, so a small ignition current turns on the auxiliary ()TO and the main GT. Full ignition is possible and the ignition characteristics are enhanced.

次にGTOeターンオフさ−虚ろにはゲート制御用W、
 R回路3のスイッチq8をオフさせるとともにスイッ
チrbをオンさせてTK崎電源Sbからスイッチゲb→
カソード電極に一+N1層→ア、十層→P6十層→オフ
電流引へ出し用ゲート電極G2→ダイオード7→外部ゲ
ート端子GO−+直流電源31′Iのループを通してオ
フゲート電離を渡し、こ八によって主GTOfcターン
オフ■せる。この時、消助GTOにはアノード電極Aか
らP1層→N1層→p、十層→N 2jQ−+補助ゲー
ト電極GA→抵抗Rジ→Pt十層→po十層→オフ電流
引き出し用ゲート電極G!→ダイオード7→外部ゲート
端子Go−+直流電源s’hへ電流が漆れる。この時抵
抗R1で生ずる電圧降下分がP2十NおよびPo” e
を介してpt 4一層とN、M9の間に逆バイアス電圧
々して印加さnるので、補助GTOを漆れる電流の一部
はP1+殿からPo十層→オフ電腑引き出し用ゲート電
極G2へと引き出される。これ((よって補助GTOが
ターンオフされる。このように補助GTOのターンオフ
時の電流は抵抗i’tf!、を全波れないので、電流の
引き出しが容易になって補助GTOの連断能力が向上す
る。この為抵抗P91を大きな値、に選定することが可
能となり、このように抵抗R91を大きな値にす1ばタ
ーンオン時の丁耐量が向上する。
Next is the GTOe turn-off - W for gate control in the void,
Turn off the switch q8 of the R circuit 3 and turn on the switch rb to connect the TKsaki power supply Sb to the switch b→
The off-gate ionization is passed through the cathode electrode through the loop of 1+N1 layer → A, 10th layer → P6 10th layer → gate electrode G2 for off-current extraction → diode 7 → external gate terminal GO- + DC power supply 31'I, and Turn off the main GTofc by ■. At this time, the auxiliary GTO includes anode electrode A to P1 layer → N1 layer → p, 10th layer → N2jQ− + auxiliary gate electrode GA → resistor R di → 10th layer of Pt → 10th layer of po → gate electrode for drawing off current. G! → Diode 7 → External gate terminal Go- + Current flows to DC power supply s'h. At this time, the voltage drop caused by the resistor R1 is P20N and Po''e
Since a reverse bias voltage is applied between the PT4 layer, N, and M9 through the PT4 layer, a part of the current flowing through the auxiliary GTO is transferred from the P1+ layer to the Po1 layer → the gate electrode G2 for extracting the off voltage. is drawn out. This ((Thus, the auxiliary GTO is turned off. In this way, the current at the time of turning off the auxiliary GTO cannot pass through the resistor i'tf!, so the current can be drawn out easily and the disconnection ability of the auxiliary GTO is increased. For this reason, it is possible to select a large value for the resistor P91, and by making the resistor R91 a large value in this way, the durability at turn-on is improved.

またこのよう((抵抗R6l全大きな値に選定してもタ
ーンオフ時の電流は抵抗R6lを流れないので遮断能力
は低下しない。さらに主GTOのターンオフ時の電流は
抵抗R92に流れないので、抵抗R□の値を適当な値に
選定してター/オフ時の点弧特性の向Fを計ることがで
きる。′I!た主GTOのター/オフ時の′M1流が抵
抗B1にがし几ないことと、ゲートドライブ回路にはツ
ェナーダイオードを不要としたことによって()Toの
ターンオフ時におけるゲートドライブ回路の電力損失が
低減される。
In addition, even if the resistor R6l is set to a large value, the current at turn-off does not flow through the resistor R6l, so the breaking ability does not decrease.Furthermore, the current at the turn-off of the main GTO does not flow through the resistor R92, so the resistor R By selecting an appropriate value for □, it is possible to measure the direction F of the ignition characteristic at turn/off.'I!'When the main GTO turns off/turns off, the 'M1 flow passes through resistance B1. Since there is no need for a Zener diode in the gate drive circuit, power loss in the gate drive circuit at the time of turn-off of ()To is reduced.

尚、前記実施例において、Pベース層中に埋込み形成さ
nた高濃度不純物層p+(はP 1 十+ Po十およ
びP2+とで構成したがこfi Ic限宇することなく
オン電流供給用ゲート電極G1の投影領域に位置するP
ベース層中にも埋込み形成しても良い。また、ゲート制
御用電源回路、3をオンゲート用電源とオフゲート用電
源とに分けるとともに、外部ゲート端子Go卦よびダイ
オード?を除去し、オン電流供給用ゲート電極() I
を前記オンゲート用電源に接続し、オフ電流引き出し用
ゲート電極G2全前記オフゲート用電源に接続するよう
に11′り成しても良い。
In the above embodiment, although the high concentration impurity layer p+ (formed embedded in the P base layer is composed of P 1 + Po + and P2+) is not limited to the on-current supply gate. P located in the projection area of electrode G1
It may also be formed embedded in the base layer. In addition, the gate control power supply circuit 3 is divided into an on-gate power supply and an off-gate power supply, and an external gate terminal Go and a diode? , and the gate electrode for supplying on-current () I
The gate electrode G2 for drawing off current may be connected to the on-gate power source, and the entire off-current drawing gate electrode G2 may be connected to the off-gate power source.

以上のように本発明によnげ、ター/オフ時のゲート電
流はP川の横方向抵抗FT、lおよびRE 11を通過
するようにしてGTOのゲートインピーダンスを大きく
するとともに、ターンオフ時のゲート電流は前記抵抗R
p I + RE2を通過しないようにしてGTQのゲ
ートインピーダンスを小さくしたので、小さな点弧電離
でGTO全点弧することができて点弧特性が向上すると
ともに、ターンオフ時の電流の引き出しが容易になって
GTOのi壱断能力が向上する。また、ターンオフ時の
電流が抵抗R1にinないことによって抵抗R9盲の値
を大きく選定することができ、これによってターンオン
時のπ耐号を高めるこ七ができる。さらに主GTOのタ
ーンオフ時の電流が抵抗R1に流れないことと、ゲート
ドライブ回路にはツェナーダイオードを不要としたこと
によってGTOOターンオフ時におけるゲートドライブ
回路の電力損失が低減さ几る等の効果が得られる。
As described above, according to the present invention, the gate current at turn-off passes through the lateral resistances FT, l and RE11 of the P river, increasing the gate impedance of the GTO, and also increasing the gate impedance at turn-off. The current flows through the resistance R
Since the gate impedance of GTQ is reduced by not passing through p I + RE2, the entire GTO can be fired with a small amount of ignition ionization, improving the firing characteristics and making it easier to draw the current at turn-off. This will improve the GTO's i-cutting ability. Furthermore, since no current flows through the resistor R1 during turn-off, the value of the resistor R9 can be set to a large value, thereby increasing the π resistance during turn-on. Furthermore, since the current does not flow through the resistor R1 when the main GTO is turned off, and the Zener diode is not required in the gate drive circuit, power loss in the gate drive circuit when the GTO is turned off is reduced. It will be done.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例のゲートドライブ回路を有する増幅ゲー
ト構造GTOの概略構成図、第2図は本発明に係る増幅
ゲートターンオフサイリスタの措成を示す説明図である
。 GTQ/・・・補助G、TOSGTO,Z・・・主GT
O1Gl・・・オン主情供給用ゲート電極、G2・・・
オフ電流引き出し用ゲート電極、0人・・・補1hゲー
ト電極、P1++ po+ I P2+・・・高O度不
純物廣。
FIG. 1 is a schematic configuration diagram of an amplification gate structure GTO having a conventional gate drive circuit, and FIG. 2 is an explanatory diagram showing the configuration of an amplification gate turn-off thyristor according to the present invention. GTQ/... Auxiliary G, TOSGTO, Z... Main GT
O1Gl...gate electrode for supplying on-state information, G2...
Gate electrode for extracting off-current, 0 person...Supplementary 1h gate electrode, P1++ po+ I P2+...High O degree impurity.

Claims (1)

【特許請求の範囲】 P+ N+ Pa Ng JF5から成る補助GTO部
と、この補助GTO部と同一ウェハ上に設けらf′1.
11.つPIN+ Po Ng層から成る主GTO部と
、前記ウニ・〜の中央部の前記−Po層表面に設けらn
たオン電流供給用ゲート電極と、このゲート電極+c対
して同心円上であり且つ前記112層とN3層を挾む位
置の前記Po層表面に設けらnたオフ電流引き出し用ゲ
ート電極と、前記オン電流供給用ゲート電極に対して同
心円上であるとともに前記N3層i−ら所定用離隔てた
外周の前記Po層表面に設けらn 、fl。 つ前記N2層に設けた電極に1妾続さ几る補助ゲート電
極と、前記N2層の投影領域に位置する前記Po層中に
狸込み形成さルた高濃度不純物層p、“と、前記N3層
の投影領域に位置する前記Po層中に埋込み形成さfL
t高濃度不純物層p 、+と、前記高濃度不純物層p、
+とP!+とを結ぶ位置の前記po層中に内端が前記P
、+に連結さn目、っ外端が前記P2+に連結さnて埋
込み形成された高濃度不純物層P。+と金備えたことを
q!j徴とする増幅ゲート jM 7* の GTO。
[Claims] An auxiliary GTO section consisting of P+ N+ Pa Ng JF5, and an auxiliary GTO section provided on the same wafer as f'1.
11. A main GTO part consisting of one PIN + Po Ng layer, and a main GTO part made of a Ng layer, and a n
a gate electrode for supplying an on current; a gate electrode for drawing an off current provided on the surface of the Po layer at a position concentric with the gate electrode +c and sandwiching the 112 layer and the N3 layer; n, fl are provided on the surface of the Po layer at the outer periphery, which is concentric with the current supply gate electrode and spaced a predetermined distance from the N3 layer i. an auxiliary gate electrode connected to the electrode provided in the N2 layer; and a high concentration impurity layer p formed in the Po layer located in the projection area of the N2 layer; fL is embedded in the Po layer located in the projection area of the N3 layer.
t high concentration impurity layer p, + and the high concentration impurity layer p,
+ and P! The inner end of the po layer is connected to the P
, +, and the outer end of the high concentration impurity layer P is buried and connected to P2+. q that you have + and money! GTO of amplification gate jM 7* with j characteristic.
JP9744483A 1983-05-31 1983-05-31 Gto of amplifying gate structure Pending JPS59220970A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9744483A JPS59220970A (en) 1983-05-31 1983-05-31 Gto of amplifying gate structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9744483A JPS59220970A (en) 1983-05-31 1983-05-31 Gto of amplifying gate structure

Publications (1)

Publication Number Publication Date
JPS59220970A true JPS59220970A (en) 1984-12-12

Family

ID=14192497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9744483A Pending JPS59220970A (en) 1983-05-31 1983-05-31 Gto of amplifying gate structure

Country Status (1)

Country Link
JP (1) JPS59220970A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997044827A1 (en) * 1996-05-20 1997-11-27 Siemens Aktiengesellschaft Thyristor with integrated du/dt protection

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997044827A1 (en) * 1996-05-20 1997-11-27 Siemens Aktiengesellschaft Thyristor with integrated du/dt protection

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