JPS59220575A - Cpu speeding preventing system in electronic lock system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for preventing CPU runaway in an electric lock system that uses a CPU to perform verification processing for pp.zeta.-locks.

[Background technology]

FIG. 1 is a schematic diagram of a conventional lock system.

In the same figure, (1) is a collation processing means, and the CPU (
It is configured by a microphone amplifier including 21. (3) is an operation panel 1D) 9, a terminal for inputting an unlock code (4), and various display codes (5). When the unlock code is input from the operation panel (3), the status change detection means (6) detects this and the CPU
The power supply means (8) supplies power from the power supply means (8) to the CPU (21) by the power-on means (7). Verification processing means including the CPU t21 (rl is the unlocking input input from the operation panel (3)) -1 The unlocking means (9) outputs a coincidence detection signal when the coincidence detection signal is input.When the coincidence detection signal is not input, the unlocking means (9) opens the electric lock (10). When the CPU (21) completes the verification processing operation, it sends a signal to the CPU power off means (11), and the CPU (21) is turned off from the power supply means (8).
Stop the power supply to.

By the way, in such an electric lock system, immediately after the power of the CPU (2+) is turned off by the CPU power off means (1), human power is applied from the operation panel (3), and the state change detection means (6) A starting pulse is output and C
When the PU power switch means (7) operates, C*P U (
Before the power supply voltage of CPU 21 falls sufficiently and the reset operation is not performed, the power supply voltage of CPU 21 increases and the operation of CPU 21 resumes. ), the power supply voltage will momentarily dip, causing the CPU (2)
causes it to go out of control. Once the CPU (i2) goes out of control, it may behave abnormally in response to human input, or it may not operate at all in response to input, or it may be inconvenient that it will no longer accept human input. was there.

[Purpose of the invention]

The present invention has been made in view of the above points,
Immediately after turning off the CPU power, do not turn on the CPU power even if a startup pulse is input.
It is an object of the present invention to provide a method for preventing runaway of C P tJ in an electric lock system in which the C P tJ is reliably reset.

[Disclosure of the invention]

The configuration of the non-explosion side will be described below with reference to the illustrated embodiment. As shown in FIGS. With the detection signal, the electric lock (1
0); an unlocking means (9) that performs the unlocking operation; a state change detecting means (6) that detects the start of an unlocking operation input and generates a starting pulse; It is equipped with a CPU power-on means (7) that turns on the CPU power when a pulse is input, and a CPU power-off means (7) that turns off the CPU power after the verification process of the input unlock code is completed. The electric lock system comprises a clocking means 02) that starts a timing operation when the CPU power is turned off and ends the timing operation after the time required for the CPU to complete the reset operation 1), and a timing means β timer. In the previous work, CPU
A CPU power control means (1) is provided to forcibly turn off the power.The time required from the start of the timekeeping operation of the timekeeping means 4 to the end of the timekeeping operation (time limit) t/'
i. CPU power off means (1)
8) It is necessary to set up a time equal to the time it takes for the power supply voltage at the power input terminal of the cPU (2) to sufficiently drop after stopping the power supply to the cPU (2). Normally, the time limit is set to about 20 milliseconds, but if a comparatively large capacity capacitor is connected to the output side of the power supply means (8), the time limit is set accordingly. It needs to be longer. In the embodiment shown in FIG. 2, the CPU f21 completes the verification process for the unlocked code and sends a signal to the CPU power off means t11).
P 15 (When the power supply to 21 is stopped, a drop in the power supply voltage is detected by the shibrator side, and the timer (14) is activated. A timing operation is performed during the time limit period, and during this timing operation period, the power supply from the power supply means (8) to the CPU (2) is controlled by the CPU power supply control means (113).
11j. Therefore, even if a startup pulse is generated from the operation panel (3) during this period, the power supply to the CPU (2) will not be restarted, and the power supply to the CPU (2+) will not be restarted. It can be reset to

FIG. 5 is a block circuit diagram of main parts in a more specific embodiment of the invention. In the figure, (12A) is a timer IC used as an IT time means (l''4), and (12A) is a timer IC used as an IT time means (l''4).
0A) is a switch means used as the CPU four-source controller control 13). Furthermore, (14A) is a Schmitt trigger circuit, (14B) is a reference voltage generator, and together they are used to generate the cibalator in the embodiment shown in FIG. Noh is realized. In this 'f13 Figure 13, C
Although only the main parts around the PU (2) are shown, the general structure other than the mounting part is the same as that shown in FIG. 2. FIGS. 4(a) to 4(d) show the respective assistant market pressure waveforms of sections a to d in the circuit of FIG. 5. - First, FIG. 4(a) shows state change human power (starting pulse). This state change human power is output from the state change detection means (6) when the operating panel (3) is operated, and has a pulse width of, for example, about 5 milliseconds. By this state change manual power (starting pulse), the power supply means (8)
Start supplying power to CPU U (21.
1. During the operation period, a busy signal (BUSY) is output as shown in FIG. 4(b). This busy signal is connected to one input of OR gate 05). Therefore, C.P.
During the period when U+21 is in operation, the power supply means (
8) ]] terminal input is held at H level, and the CPU
(The power supply to 2+ is continued. When the CPU (2) finishes its operation, the busy signal falls to the L level, so the cositroll input of the power supply means (8) also becomes the L level. At this time, the power supply CPU from supply means (8)
(The voltage supplied to the 4-source input terminal vDD of 21 is shown in Figure 4 (
It decreases as shown in C). This voltage drop is detected by a comparator circle consisting of a Schmitt trigger circuit (14A) and a reference voltage generator (14B), and a timer IC (12A) is activated by the detection output. The timer IC (12A) maintains its output at H level for a time limit of approximately 20 milliseconds after the start of the timing operation. Therefore, even if there is 10 manpower and a starting pulse occurs during this period,
The output of timer I'C (12A) makes it easy.
Since the power supply means (13A) is turned on, the power input is pulled to the L level as shown in FIG. 4(d), and the power supply from the power supply means (8) to the CPU (21) is Power is not supplied. In this case, the CPU (2+) can always be reset reliably. As a comparative example, FIG. As shown in the figure, in the case of the conventional example, the starting pulse (Fig. 4 (b)) is activated immediately after the start pulse (Fig. When a)) is input, the CPU
(Power supply voltage of 2+ (Fig. 4 (c)) i'l: There is a risk that the voltage will rise again before it falls sufficiently and cause an abnormality in the operation of the CPU (21). However, in the present invention, such a problem can be avoided. It is completely resolved.

By the way, in general, in order to prevent the CPU (21) from running out of control, fluctuations in the power supply voltage of the CPU (2) are detected and the CPU
, U(2) operating voltage 111i2. When supinated, CPU (c'P U that reset 2+ and went out of control)
(Returning 21 to its original state has been done for some time, but the present invention is completely different from such a general CPU runaway prevention method.
As shown in the figure, this is a so-called system that has a CPU power supply switch (7), a CPU power supply switch (+1), etc., and supplies power to the CPU +21 only when the electric lock system requires processing. This is a runaway prevention method for the CPU (+2) used in a power-saving electric lock system, and when the power supply voltage supply to the CPU (2) is stopped, immediately after that, there is a 10-man power and a starting pulse is generated. This is a novel invention whose main point is to prevent the supply of power supply voltage from being restarted until the reset operation of the CPU +21 is completed even if a reset operation occurs, so that the reset operation can be performed completely. Incidentally, an electric lock system using such a power saving method is particularly useful when used in applications where it is necessary to save power consumption as much as possible, such as when using a battery as a power source.

〔Effect of the invention〕

The present invention is configured as described above, and in an electric lock system in which power is supplied to the CPU only when performing verification processing, a timekeeping operation is started when the CPU power is turned off, and a CPU reset operation is performed. A timer that ends the timer operation after a certain amount of time has elapsed, and a CPU that forcibly turns off the CPU power during the timer's timer operation.
Since the CPU is equipped with a power supply control means, once the power supply to the CPU is stopped, the supply of power supply voltage will not be restarted until the CPU is completely reset. Even if a startup pulse occurs immediately after the supply of power supply voltage to the CPU is completely stopped, the CPU will be restarted immediately as in the conventional case, and therefore the power supply voltage of the CPU will decrease. This prevents failures such as instantaneous low voltage, and reduces C due to fluctuations in power supply voltage.
This has the effect of preventing PU from running out of control.

[Brief explanation of the drawing]

Figure fJ1 is a schematic diagram of the original structure, Figure 2 is a schematic diagram of an embodiment of the present invention, Figure 6 is a circuit diagram of the main parts of another embodiment of the above, and Figure 4 is a schematic diagram of the same embodiment. ! Wandering is shown in the above-mentioned cutting and setting] figure. fi+ is a collation processing means, (2) is a CPU, Fil is a state change conventional means, (7) is a cpu'4s on means, (9)
is an unlocking means, (10) is an electric lock, (l is a CPU power off means, (12J is a clock means, t'3) is a CPU power supply number,
fttlJ control means. Agent Patent Attorney Ishi 1) Choshichi

Claims (1)

[Claims] (The 11CPU performs verification processing of the unlocking code, the matching detection unit 1U performs the unlocking operation of the electric lock, and the start of the manual unlocking operation is detected. means for turning on the KCPU power when the starting pulse is input from the state change detecting means; and means for turning off the CPU power after verification processing of the input unlock code is completed. In the electric lock system, the timekeeping means starts the timekeeping operation when the CPU power is turned off and ends the timekeeping operation after the time required for the CPU to complete the reset operation;
1. A CPU runaway prevention method in an electric lock system, comprising CPU power control means for forcibly turning off the CPU power during the timekeeping operation of the timekeeping means.