KR0134250Y1 - Data protecting circuit - Google Patents

Abstract

The present invention relates to a data loss prevention circuit, which is generated by operating a power switch or a keyboard during system operation in order to solve the problem that data stored in a pause is lost when a power switch is operated under a conventional pause state. A first power control signal output means for outputting a control signal for turning on the output of the DC power supplied to the system according to the signal, and a DC power input according to the control signal output from the first power control signal output means to the system; A power supply means for converting into a required DC power supply and supplying power only to a required portion of the logic and outputting a power signal at that time; and a power-off clock output through a power switch or keyboard operation of the first power control signal output means. Output from power supply means according to clock signal of power off among signal and pause signal A second power control signal output means for latching the output power signal and outputting a control signal for turning off the output of DC power through the power supply means, and a battery according to the pause signal output from the second power control signal output means. By providing a data loss prevention circuit composed of a power supply control means for controlling a power supply, it is possible to prevent the loss of important data due to user's carelessness in a system having a pause function such as a notebook.

Description

Data Loss Prevention Circuit

1 is a conventional data loss prevention circuit diagram.

2 is a data loss prevention circuit diagram according to the present invention.

3 is a flowchart illustrating a power on / off and suspend / resume process according to the present invention.

* Explanation of symbols for main parts of the drawings

10: first power control signal output means 11: power supply level holding unit

12: stop stop generator 13: first latch portion

20: second power control signal output means 21: DC power output control unit

22: power off and pause signal generator 30: power supply means

40: power supply control means 41: battery power supply

42: first power supply control unit 43: constant voltage unit

44: second power supply control unit

The present invention relates to a power switch operation when pausing and resuming from a personal computer (PC), and more particularly, to a data loss prevention circuit for preventing data loss due to inadvertent power-off of a power switch in a suspended state of a PC. will be.

The prior art configuration, as shown in Figure 1, the power switch 18 for controlling the power on / off of the system, and the constant voltage unit 43a for outputting the power supplied from the battery at a constant voltage level And a first field effect transistor (FET1) for controlling a logic power supply (+ 5V) which is not used at the time of suspend, and a power supply for supplying power by converting a DC voltage into a desired DC voltage. A supply means 30 and a first transistor TR1 for controlling the power supply means 30 on / off.

For reference, the power plane of a system with a suspend function is generally divided into two planes.

In other words, it is divided into parts that need power supply and parts that are unnecessary when paused.

Accordingly, in the present invention, for convenience, the power required for pausing is displayed as + 5VS, and the unnecessary power for pausing is displayed as + 5V.

On the other hand, in the above operation, when the power switch 18 of the system is turned on, the first transistor TR1 is turned on by the power supply of the main battery VBATT or the auxiliary battery 41a, and the power supply means 30 is supplied. Power supply + 5VS required for the system is output when the system is paused, and the logic of the first field effect transistor FET1 is operated at + 5V because the gate signal is turned low by the resistor R7. Will also supply power.

In addition, when the PC enters the paused state by a pause switch or a keyboard shortcut, data required for resume is stored, and finally a high signal is recorded in the pause signal shown in FIG. The power supply + 5V, which supplies only the required power supply + 5VS at the time of suspension and the unnecessary logic at the time of suspension, is cut off by the first field effect transistor FET1 which is turned off.

The power switch 18 turns the system on / off as well as the power on / off regardless of whether the system is not suspended.

Therefore, when the power switch 18 is operated under the pause state, there is a problem that data stored at the time of pausing is lost.

The present invention aims to provide a data data loss prevention circuit for preventing data loss due to user carelessness during suspension by fully controlling dual power-on sequence and power-off sequence to solve the above problems. .

The configuration of the present invention for achieving the above object is a control signal for turning on the output of the DC power supplied to the system according to the signal generated by the operation of the power switch or the keyboard during system operation, as shown in FIG. The first power control signal output means 10 for outputting the output power, and the DC power inputted in accordance with the control signal output from the first power control signal output means 10 is converted to the DC power required for the system logic required Power supply means 30 for supplying power only at the same time and outputs a power signal at that time, and a power off signal and a pause signal output through a power switch or keyboard operation of the first power control signal output means 10. The latch outputs the power signal output from the power supply means 30 according to the power off signal to turn off the output of the DC power through the power supply means 30. Second power supply control signal output means 20 for outputting a control signal for the power supply control means 40 for controlling the battery power supply in accordance with the pause signal output from the second power control signal output means 20 It is composed of.

The first power control signal output means 10 includes a second transistor TR2 and a resistor to maintain and output a power signal output from the auxiliary battery power supply V-PWR at a constant power level required for a logic element. A pause clock generator for generating a pause clock by logically operating the pause signal by the power switch 12a and keyboard operation; and a power level holding section 11 composed of R8 and R9 and a condenser C2. 12) and latches the data of the power signal output from the power level holding section 11 according to the pause clock output from the pause clock generation section 12 to output the DC power output of the power supply means 30. A control signal for turning on and a first latch section 13 for outputting this control signal to the clear (CLR) terminal of the third latch section 21a.

The pause clock generation unit 12 includes a first NAND gate 12b and a first Schmitt trigger element 12c for logically inverting and outputting a signal by keyboard operation (shortcut key operation), and the first Schmitt trigger element ( And a second Schmitt trigger element (12d) which outputs the output signal through 12c) and the output signal by the power switch 12a operation by performing an AND logic output.

The second power control signal output means 20 is a third Schmitt trigger element 22a for logically inverting the clock signal generated by the pause clock generator 12 of the first power control signal output means 10. ) And a signal determined by the main chipset 22b and the main chipset 22b which determine a signal state to be latched by receiving the pause signal inverted through the third Schmitt trigger element 22a. Power-off and pause signal generator 22 including a second latch portion 22c for latching the state and outputting a pause signal SUSPEND and a power off signal PWR_OFF for turning off the power of an unused portion. And the power signal PWRGD output from the power supply means 30 in accordance with the power off signal PWR_OFF output from the second latch portion 22c of the power off and pause signal generator 22. And third latch portion 21a for outputting A fourth Schmitt trigger element outputting to the clear terminal CLR of the first latch part 13 to turn off the DC power output of the power supply means 30 by logically inverting the signal output from the part 21a. And a DC power supply output control unit 21 including a 21b.

In addition, the power supply control means 40 is a battery power supply unit 41 for outputting the power supplied to the system from the main battery (VBATT) or the auxiliary battery (41a) through the diode (41b, 41c), and the battery power supply unit From the battery power supply unit 41 and the first power supply control unit 42 including the resistors R15 and R18 and the third transistor TR3 to cut off and control the power output from the 41 in normal operation. It is connected to the constant voltage unit 43 for maintaining and outputting the output voltage at a constant voltage and the pause signal SUSPEND output from the second latch unit 22c of the second power control signal output unit 20. In order to supply and control the power output from the constant voltage unit 43 to the unnecessary parts and the entire system in a normal operation, the second power supply control unit 44 configured as the second field effect transistor FET2 is provided.

Referring to the operation of the present invention by the configuration of the embodiment as follows.

First, as shown in FIG. 2, the power V_PWR output from the auxiliary battery includes the second Schmitt trigger 12d, the first latch part 13, the third latch part 21a, and the third and fourth Schmitt trigger elements ( 22a and 21b, respectively, to maintain the power supply level required by the logic signal element through the power supply level maintaining section 11, respectively.

Accordingly, when the power switch 12a is turned on to supply power to the system, since the power switch 12a is a push button, a low pulse signal is transmitted to the second Schmitt trigger element 12d, and the second Schmitt trigger element ( The output of 12d) is that the inverted high pulse signal is transmitted to the clock terminal CK of the first latch unit 13 so that the power supply of the first latch unit 13 is applied to the rising edge of the clock terminal of the first latch unit 13. The signal (high signal) is transmitted to the power supply means 30.

Accordingly, + 5VS is output from the power supply means 30 and is supplied to the power supply control means 40.

On the other hand, the main chip set 22b keeps the predetermined values of the output power off signal PWR_OFF and the suspend signal SUSPEND of the second latch portion 22c until they are initially initialized.

In addition, when the system is powered on and the keyboard is pressed by a keyboard (shortcut key), the system's keyboard controller recognizes this and presses the keyboard's pause key (for example, Fn + SUSPEND) during system operation. If the KBDSRBTN * is notified of entering into the pause state, the first NAND gate 12b, the first Schmitt trigger element 12c, the second Schmitt trigger element 12d, and the third Schmitt trigger element 22a are used. The chip set 22b is delivered, and the received system takes the necessary steps to enter the paused state.

In other words, the data and state necessary for resumption are stored in the memory or CMOS area, and then the output ports Q1 and Q2 of the second latch portion 22c are turned off in order to finally turn off the power of the unused portion during the pause. Record the high signal value.

Then, by writing a high signal to the output terminals Q1 (PWR_OFF) and Q2 (SUSPEND) in the second latch portion 22c, the clock terminal CK of the third latch portion 21a changes from a low state to a high state. At this time, the power signal PWRGD of the high state output from the power supply means 30 is transmitted to the output terminal Q of the third latch portion 21a, which is then latched to the first latch through the fourth Schmitt trigger element 21b. By applying a low signal to the clear terminal CLR of the unit 13 and clearing it, a low signal is output. The power supply means 30 is turned off, and the DC power supply + 5VS and the power signal PWRGD become low.

At this time, since the output (low signal) of the first latch portion 13 is connected to the clear terminal of the third latch portion 21a, the output of the third latch portion 21a is set to the low first state. The operation of the power control signal output means 10 is performed smoothly.

At the same time, the third transistor TR3 is operated by the suspend signal SUSPEND, which is the output of the second latch portion 22c, to operate the constant voltage regulator 43a, and the output at this time is the main battery VBATT or negative. + 5VS is supplied by the battery 41a, while the second power supply control unit 44 using the second field effect transistor FET2 does not output +5 by the pause signal.

Accordingly, there are two processes in resuming operation from the pause state.

That is, the method by the keyboard (KBDSRBTN *) and the power switch 12a, which distinguishes this method from the keyboard that the keyboard has sent a signal to the system by the keyboard controller when the keyboard is restarted. This is possible by passing the data to the system BIOS by the BIOS, and thus by reading this value upon restart.

Therefore, in the resumption process by the keyboard controller, when the keyboard is first pressed, the keyboard controller outputs a low pulse signal to the system to the keyboard operation signal KBDSRBTN *, and the first NAND gate 12b and the second NAND Schmitt trigger ( 12c), the power supply means 30 is turned on through the second NAND Schmidt trigger 12d, and when the system enters the main chipset 22b through the third NAND Schmidt trigger 22a, the system performs the resumption process. In this case, the first thing to do is to turn on the power, as the last time the power was turned off when pausing.

That is, the + 5V power is turned on by writing a low state value to the output ports Q1 and Q2 of the second latch portion 22c.

Power supply means through the first NAND gate 12b, the first Schmitt trigger element 12c, the second Schmitt trigger element 12d, and the first latch portion 13 by the keyboard operation signal KBDSRBTN *. 30) is on.

When the power state is stable, the resume process is completed by restoring the value that was saved to bring it to the state just before entering suspend.

On the other hand, the process of turning on the power supply means 30 and the process of turning on + 5V when the power switch 12a is pressed in the pause state is the same as the resumption process by the keyboard, but the one switch 12a is added to this process. Operation is resumed, so it is necessary to check whether the power is off or not.

That is, when the power supply means 30 is turned on by the power switch 12a, and it is transmitted to the main chip set 22b through the second Schmitt trigger element 12d and the third Schmitt trigger element 22a, the system BIOS (BIOS) checks whether this is by the power switch 12a or the keyboard (the value transmitted by the keyboard BIOS). When the power switch 12a is used, the BIOS checks whether the monitor is powered off. Regardless of the previous state, the power supply means 30 is turned off by writing a low signal to the output port Q1 of the second latch portion 22c. If not, the previous state is performed as in the case of resumption by the keyboard. To recover.

This power on / off and suspend / resume process will be described with reference to FIG.

First, it is determined whether the power switch 12a is pressed by the user, and when it is pressed, it is determined whether the document processing operation is finished after processing the document.

When the document processing operation is not finished, it is determined whether the pause key is pressed, and when the pause key is pressed, the power off (PWR_OFF) and the pause signal (high signal) are recorded.

After the recording, it is determined again that the power switch 12a has been pressed, and when the power switch is pressed, the user is asked to turn off the power, and when the user logs off the signal that the user turns off, the power is turned off if the power is not turned off. After recording (PWR_OFF) and the pause signal (low signal), the above document processing operation is performed.

On the other hand, it is determined again that the power switch 12a is pressed, and if the power switch is not pressed, it is determined whether the keyboard is pressed, and when the keyboard is pressed, the power off and pause signal (low signal) is recorded.

As described above, the present invention checks the state before operating the power switch in a portable computer product having a pause function such as a notebook, and in the case of a pause state, the previous state is temporarily stopped by checking whether the user wants to turn off the power. It is effective to prevent inadvertent loss of important data by notifying that it has been stopped and confirming whether or not to save the state data before suspension.

Claims (5)

First power control signal output means for outputting a signal for controlling the output of DC power supplied to the system according to a signal generated by operation of a power switch or a keyboard during system operation, and output from the first power control signal output means Power supply means for supplying the DC power inputted according to the control signal to the system and outputting the power signal at that time; and the power on / off output through the power switch or keyboard operation of the first power control signal output means. A second power control for outputting a control signal for turning off the output of the DC power through the power supply means by latching the power signal output from the power supply means according to the clock signal of the power on / off signal among the clock signal and the pause signal; Battery power supply according to the signal output means and the pause signal output from the second power control signal output means. Power supply control means for controlling the power supply, power supply control means for controlling the battery power supply according to the pause signal output from the second power control signal output means, and a keyboard operation so as to control the second nuclear power control signal output means. And a BIOS for determining whether the power switch is pressed. The power supply level holding unit (11) according to claim 1, wherein the first power supply control signal output means (10) maintains and outputs a power signal output from an auxiliary battery power supply at a predetermined power supply level required for a logic element; The pause clock generator 12 generates a pause clock by logically operating the pause signal generated by the switch 12a and the keyboard operation, and the data of the power signal output from the power level maintaining unit 11 is temporarily stored. A control signal for turning on the DC power output of the power supply means 30 by latching in accordance with the pause clock output from the stop clock generator 12 and outputting the control signal to the clear terminal of the third latch portion 21a. And a first latch unit (13). 3. The pause clock generator 12 further includes a first NAND gate 12b and a first Schmitt trigger element 12c for logically inverting and outputting a signal generated by a keyboard operation, and the first Schmitt trigger. And a second Schmitt trigger element (12d) which outputs the output signal through the element (12c) and the output signal by the operation of the power switch (12a) by a negative value. The second power control signal output means 20 further comprises: a third Schmitt trigger element 22a for logically inverting the clock signal generated by the pause clock generator 12; A main chip set 22b for receiving the inverted pause signal received through the third Schmitt trigger element 22a to determine a signal state to be latched, and latching and pausing the signal state determined through the main chip set 22b. A power-off and pause signal generator 22 including a second latch portion 22c for outputting a signal and a power-off signal PWR_OFF for turning off power of an unused portion, and the power-off and pause signal The third latch unit 21a which latches and outputs the power signal PWRGD output from the power supply unit 30 according to the power off signal PWR_OFF output from the second latch unit 22c of the generator 22. ) And a signal output from the third latch portion 21a. To a DC power output control unit 21 including a fourth Schmitt trigger element 21b which is reversed and output to the clear terminal of the first latch unit 13 to turn off the DC power output of the power supply means 30. Data loss prevention circuit, characterized in that configured. The battery power supply unit 41 of claim 1, wherein the power supply control unit 40 outputs power supplied to the system from the main battery VBATT or the auxiliary battery 41a through the diodes 41b and 41c. A first power supply control unit 42 which cuts off the power output from the battery power supply unit 41 during a normal operation, and a constant voltage unit which maintains and outputs a voltage output from the battery power supply unit 41 at a constant voltage ( 43) and a second portion which is supplied with the pause signal output from the second power control signal output means 20 to supply and control unnecessary parts output from the constant voltage section 43 to the entire system during normal operation. Data loss prevention circuit, characterized in that consisting of the power supply control unit (44).