JPS59219783A - Display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a display device having a bitmap memory capable of performing highlighted display such as blinking and inversion.

[Technical background of the invention and its problems]

BACKGROUND ART In a display device, one method for emphasizing information such as displayed characters is a blink display in which characters to be emphasized are displayed by blinking them at a constant cycle. Another method is an inverted display in which the black and white of characters to be emphasized are inverted.

Memorize the character codes to be displayed in the order in which they will be displayed,
A method is conventionally known in which the character code is provided with one or more highlighting control bits, which are simultaneously read out and converted into character dots)/F turns for highlighting. However, this rough display control has the disadvantage that it is not possible to perform pixel-by-pixel display required for graphic displays and the like.

On the other hand, some display devices capable of displaying graphics have a bitmap memory.

However, in the case of a bitmap memory, a device that performs highlighting such as blinking on displayed characters must have a highlighting control memory that corresponds to every bit of the bitmap memory in a one-to-J ratio. However, since it requires a large capacity memory, the device becomes large and expensive.

[Summary of the invention]

In order to achieve the above object, the present invention provides a register in which a character display area is defined and set by 10 sets,
The address (coordinate value) set in the register is compared with the address output from the display timing control section, and the comparison result indicates that there is an asserted bit in the bitmap memory. Configure this bit to be considered a highlight control bit only if
It performs display modification operations such as inversion and high-intensity display.

This allows you to set the character display area that can be highlighted and the area that can display graphics, and also allows you to modify the text without needing a separate memo 17k for highlighting control. A graph ink display capable of controlling the φ display can be provided.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing an entire embodiment of the present invention. In the figure, No. 1 is a display timing control section. The display timing control unit 11 sequentially generates addresses (RADR) of the bitmap memory 13 in which display information is stored in accordance with the television rough scan, and generates each column cloth INN number necessary for display control. do. 12 is a selector. Selector 12rJ% display timing control unit 11 output address (RADR) Tobitmanop memory 13
In order to update the contents, a control device such as a microprocessor (not shown) selects one of the output addresses (WADR) and outputs it to the bitmap memory 13.

Reference numeral 13 denotes a bitmap memory in which display information is stored in the form of 612 dot images.
The blue report is output and displayed by the fi 111 section 11. 14 is a register newly added according to the present invention. The register 14 holds coordinate values of a character display mode area output by a microprocessor or the like. 15 is a comparator. The output of the display control section 11 and the output of the register 14 are supplied to the comparator 15, and a step 716 determines whether or not the address generated at the display timing 11 exists within the area defined by the register 14. This is a video signal generator. The video signal generator J is above the comparator J-
Bitmap memory 13 whose output is significant
A specific bit of the output is regarded as a highlight display control bit, and all highlight display controls are performed and sent to a display device (not shown) as a bit-serial video signal.When no signal is output to the comparator plate, the bitmap memory 13 All of the outputs are directly converted into bit-serial video signals and sent to a display device (not shown).

FIG. 2 is a block diagram showing an embodiment of the comparator shown in FIG. 1.

In the figure, numerals 151 to 154 are converters for determining the magnitude of inputs A and B. If A > 13 here, then V
When A=H, the signal is output to the = terminal, and when A (B, the signal is output to the △ terminal. 156 and 157 are the outputs of controllers and regulators 151 and 153, respectively. A=B and A<H, respectively.
or dart to generate a logical OR output of the output signals of , 155
Figure 3 is an embodiment of the video signal generating section 16 shown in Figure 1.

In the figure, 161 is a register that temporarily stores the output of the bitmap memory 13, 162 to 166 and 169 are AND dates, 167 and 110 are inverters that output signals with the opposite polarity of the input, and 168 is a register that converts 9 parallel information into a bit serial format. The shift register 171 that converts into information is an EQR gate that generates an exclusive OR output.

FIGS. 4-7 are diagrams cited to illustrate the operation of the present invention. FIG. 4 is a diagram showing the position on the display screen of the character display area defined according to the present invention. Figure 5 (a
) e (b) and (e) are operational conceptual diagrams expressing the operation of the embodiment of the present invention on a bitmap memory or a display screen, and each shows the contents of the bitmap memory 13 (
(b) Display form of data A displayed on the display screen when the comparison Er15 output is 1'' and the specific bit (*) of the bitmap memory 13 is '1''.

The display form (c) of f-tater A displayed on the display screen when the output of the comparator 215 is '0' or the specific bit (*) of the bitmap memory 13 is '0#' is shown.

FIG. 6 is a diagram showing the correspondence relationship between the display screen and the bitmap memory.
The reference is to a display device whose screen is composed of 640 dots. Figure 7 shows the at L/L supplied to the bitmap memory.
FIG. 2 is a diagram showing the timing relationship between data (ADR) and obtained information (DATA).

The operation of the present invention will be explained in detail below. Display timing control unit 11 As shown in the 6th line, the addresses of the corresponding pin r map memos 1 and 13 of the display screen K are outputted in accordance with the television last scan. The normal selector 12 is the address (RAT) output by the display timing control section 11.
R) 'fr- Operates to output to the bitmap memory 13. Here, the timing relationship between the address (RADR) and the read bit map memory information is as shown in FIG. As shown in the figure, 11 negative addresses from "0#" to "79#" are output as the selector 12 output, and a retrace period continues, forming one scan. This scanning line is 400
The book is formed. The last scan line has address 31920
The bitmap memory 13 outputs are sequentially output from ``31999'' to ``31999'', and then the retrace period ends and the scanning returns to the first scanning line.
), . . . , the contents of addresses θ, 1, etc. are outputted and transmitted to the video signal generator 16, as expressed as , . , is set in register 14. This value is determined by the display timing control section 11 depending on the comparator.
is compared with the address output by . This comparison operation will be explained in detail using FIGS. 2 and 4. Coordinate values I/'i, (Xt-Yx), (x 2 e
Y 2 ). The area defined by these coordinate values is controlled by comparators 151 to 154, or darts 156 and 157, and an AND gate 155 so that the area is divided as shown in FIG. Therefore, while the address (RADR) is in the relevant area, the AND gate 155 output becomes significant.

The operation of the video signal generator 16 will be explained with reference to FIG. Information read from bitmap memory 13 is temporarily set in register 161. The signal is then transferred to a shift register 168 and converted into a serial video signal by a clock pulse (not shown). Now, when the character display area signal (output from the comparator 15) is output, the input condition for one of the AND gates x6x and 1es is satisfied.

If bit <7> of register 161 is 1゛1'', the output of gate 165 becomes °1'', so E
Niji on OR date 171, original information bit 6〉~
In <1>, a video signal with black and white inverted is generated.

If bit <7> of register 161 is “0”, unr
Date 165 output is “0#”, so the original information (D
Bits (6) to (1) of ATA) are generated as a video signal with the same polarity. This situation is shown in Figure 5(a).
, (b) and (e).

On the other hand, if bit <0> of register 16 is 1',
When the AND gate 162 is turned on, the signal "1#" is supplied to one input terminal of the AND dart 166.
-) The other input terminal of J e 6 has Q
'J/ OFF i Repeat clock pulse (CLK)
is supplied, and as an AND gate 166 l', n
A repeating signal of Os is generated and output. Furthermore, the inverter 170 connects one terminal of the Cyan date 169 to 0'',
'1# repetition signal is supplied, so the bit serial signal of the shift register 168 is periodically dated by the AND gate 169, and becomes a video signal with blink display modification.Next, the 5 character display area signal (comparison 15 output) is not output, the AND gate 163e164 is turned ON, and the entire output of the register 161 is transferred to the ``!, MA shift register 168, and becomes a bit-serial video signal as it is.In this case, It becomes possible to display graphs, images, etc. in pixel units.

The video signal generated in the above manner is the EOR gate 1.
71, the signal is sent to a display along with a periodic signal (not shown), and desired information is displayed.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to set all the text display areas that can be highlighted and the areas that can be displayed with graphics.
Furthermore, it is possible to provide a display device having a bitmap memory that does not require a separate memory for highlighting control.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an embodiment of the comparator in FIG. 1, and FIG. 3 is a block diagram showing an embodiment of the video signal generator in FIG. 1. Figures 4 and 4 are diagrams showing the position of the character display area defined by the present invention on the display screen, and Figures 5(a) and 5(b).
) + (c) is an operation conceptual diagram 1 expressing the operation of the embodiment of the present invention on a bitmap memory or a display screen, FIG. 6 is a diagram showing the correspondence between the display screen and the bitmap memory, and FIG. 7 1 is a diagram showing the timing relationship between the address supplied to the bitmap memory and the information obtained. 1--Display timing control unit, 12--Selector, 13--Bit map memory, 14--Register, 15--Comparator, 16--Video signal generation section. Llj lr Single agent Patent attorney Suzue Takehiko
Flight 6 Figure 1 Figure 14 Figure 2- Figure 3 Figure 4

Claims (5)

[Claims] (1) Number of pit map memory memories that store display information A display timing control section that sequentially generates addresses and reads information from the bit map memory in accordance with the display order, external coordinate values are set, and character display areas are kept defined. a comparator that determines whether or not the address value generated and output by the display timing control section 1 exists within the area held in the register and outputs the result, and the comparator When there is an output state, the above bitmap memory output is used as a video signal as it is, and only when it is in another state and a specific bit of the above bitmap memory indicates a certain state, this bit is used as a highlighting control bit. A display device, characterized in that it is completely equipped with a display control section for emphasizing the output of the bitmap memory. (2) The display device according to claim 1, wherein the display device performs a blink display as a highlighting control function. (3) The display device according to claim 1, wherein the display device performs inverted display as the highlighted display control function. (4) The display device according to claim 1, wherein the display device performs high-intensity display as a highlighted display control function. (5) The display device according to claim 1, wherein the display device performs color display as the highlighting control function.