JPS59218578A - Fft address generating device - Google Patents

Abstract

PURPOSE:To execute a bit inversion access at a high speed by bit-inverting directly an output of a numerical arithmetic circuit, and thereafter, shifting it by a necessary bit number by a barrel shifter, and fetching a necessary data by one cycle. CONSTITUTION:A numerical arithmetic circuit 72 and 73 execute an arithmetic respectively, basing on a data inputted through an initial value data bus, and output its result. An output of the numerical arithmetic circuit 72 is inputted directly to an adder 77. On the other hand, as for an output of the numerical arithmetic circuit 73, one of a case its output is not bit-inverted (namely, the output of the numerical arithmetic circuit 73 as it is) by a selector 75 and a case it is bit-inverted is selected. A data selected by the selector 75 is shifted by a barrel shifter 76, and thereafter, added to the output of the numerical arithmetic circuit 72 in the adder 77, and for instance, ouputted as an FET address to an output data bus 78.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an arithmetic device that generates addresses for input and output data in fast Fourier transform (hereinafter also referred to as 1-Fl''Tj).

[Technical background of the invention and its problems]

Radix-2 butterfly operation and u in fast Fourier transform
The operations performed are shown in FIG. If a and b in the same figure are respectively input data (A+iB), (C+iD) and (), and C is coefficient data of (X+iY), the output data d and e are as follows.

(A+(CX-DY) l+ i (B+(DX+CY)
) 1・・・・・・・・・・Output data d (A-(CX-DY)l+1(B-(DX+CY))・
......Output data e is obtained. This is the butterfly operation.Based on such a butterfly operation, the data flows of the time thinning and frequency thinning algorithms in the one-dimensional fast Fourier transform of base 1ji2 are shown in Figures 2 and 6, respectively. show.

Here, the number of sample points shown in FIG. 2 is 8. Addresses generated by the temporal bow 1 algorithm in a radix-2 one-dimensional fast Fourier transform are shown in Table 1.

Table 1 Further, the addresses generated by the frequency thinning algorithm in the one-dimensional fast Fourier exchange of radix 2 shown in FIG. 6 are as shown in Table 2.

[Margin below]

Table 2 X in each of Tables 1 and 2. (k) → x, (
k) , x2(k) 4 Looking at the data in Table 1.

It can be seen that the bits of the input data and output data in each of Table 2 are inverted (this is referred to as bit inversion). Then, by repeatedly applying the algorithm of FIG. 2 or 6 to horizontal and vertical data as shown in FIG. 4, it can be extended to two-dimensional fast Fourier transform. still.

Figure 1 is two-dimensional data (8x8), and 2 to 17
is one-dimensional FFT input data.

By the way, regarding the bit reversal access, F F
The number of pits to be reversed differs depending on the number of T points. To explain this using FIG. 5, for example, the number of FFT points (number of bits) is 8 (= 2") and 1024 (= 2").
10), 2n, the number of bit inversion bits is 3, 10, . n, and each is different.

Furthermore, when performing a two-dimensional FFT operation on two-dimensional data 2n×2m, it is necessary to separately invert the upper n bits and the lower m bits, as shown in FIG.

Conventionally, the following two methods have been used to separately invert the upper n bits and lower m bits.

That is, the first method is to obtain the value using software calculations including judgment instructions, and the second method is to obtain the value by shifting the nodes one bit at a time.

However, in either of the first and second methods described above, high-speed access by bit reversal cannot be expected, and the high-speed performance of fast Fourier transform is halved.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an FFT address generation device that can perform bit reversal access at high speed.

[Summary of the invention]

The outline of the present invention for achieving the purpose of recording MJ is as follows. a second calculation means, a selector for bit-reversing the output of the second calculation means, a barrel shifter for shifting the output of the selector, and an addition for adding the output of the first calculation means and the output of the barrel shifter. The present invention is characterized in that it has a means for performing bit reversal high-speed access.

[Embodiments of the invention]

An embodiment of the invention will be described below with reference to the drawings.

FIG. 7 shows l! according to the present invention. 71 is a block diagram of an F T address generation device. 71 in the same figure is, for example, an initial value data bus, and a numerical calculation circuit 72 which is the calculation means of nest 1, and a second calculation means, such as 11, which is a calculation means of nest 1. These numerical calculation circuits 72 and 73 each include, for example, a register *a and one numerical calculation unit. The output side of the numerical calculation circuit 72 is connected to one input side of an adder 77, which is an adding means, and the output side of the numerical calculation circuit 66 is is connected to the selector 750 input side.

Here, the details of the connection relationship between the numerical arithmetic circuit 76 and the selector 75 are shown in FIG. 8 (however, for convenience, the case of 4 bits is shown). As shown in the figure, the output side of the numerical calculation circuit 76 is connected to one input side of a selector 75 having, for example, two operators, and is connected to the selector 75 via a bit inversion bus 74 whose connection arrangement is reversed. connected to the other input side of the In this way, the numerical calculation circuit 76 and the selector 7
5, for example, when the output of the numerical calculation circuit 76 is rololJ, rololJ is input to one input side of the selector 75, and rloloJ with bits reversed is input to the other input side. be done.

The selector 75 (Figure i7) selects one of the two systems of data input to the selector 75, and its output side is connected to the input side of a barrel shifter 760 disposed at the subsequent stage. . The barrel shifter 76 can shift the output data of the selector 75 by an arbitrary number of bits, and its output side is connected to the other input side of the adder 77.

This adder 77 adds the output of the barrel shifter 76 and the output of the numerical calculation circuit 72, and its output side is connected to an output data bus 78.

Further, the numerical calculation circuits 72, 73. The selector 75, barrel shifter 76, and adder 7 are each connected to a control means (not shown), and their operation timings are controlled according to a predetermined program.

Next, the operation of the FFT address generator configured as described above will be explained.

First, numerical arithmetic circuits 72 and 76 each perform arithmetic operations based on data input via the initial value data bus, and output the results. The output of the numerical calculation circuit 72 is directly input to the adder 77. - For the blade numerical value 6ii and the output of the arithmetic circuit 76, the selector 75 selects either the case where the bits are not reversed (that is, the output of the numerical arithmetic circuit 7) is unchanged, or the case where the bits are reversed. The data selected by the selector 75 is shifted by a barrel shifter 76, and then added to the output of the numerical arithmetic circuit 72 in a booster 77 and sent to the output data bus 78, for example, by h'
Output as FT address.

Next, assuming that the FFT address generation device according to the present invention described above is, for example, an 8-bit system, a radix-2 time thinning FF
An example in which the T algorithm is applied to 4×80 two-dimensional data will be described.

First, Table 6 shows the addresses of the two-dimensional data.

Addresses in the table are expressed in octal notation.

Table 6 (blank space below) Here, 191] is applied to the data in the address space, and if an FFT algorithm is applied to the data in the horizontal direction, in which the lower 6 bits of the address are subject to bit reversal,
A one-dimensional FFT in the diagonal direction can be realized, and a two-dimensional FFT can be realized by applying an FFT algorithm that subjects the upper two pits of the address to bit reversal to data in the vertical direction.

Next, in such two-dimensional data, F according to the present invention
Table 4 (in the following margins) shows the FFT input card address generated when the FT address generator performs bit reversal in the horizontal direction of the address space. Further, Tables 5 and 6 show FFT input data addresses generated when the transition time t is continuous and bit reversal is not performed. Here, all the numbers in Tables 4 to 6 are in octal numbers except for the time, R means the first address of the real part (REAL PA 几T), and 1 means the imaginary part (I MAGI NARY PA 几T). ) means the first address.

Regarding Tables 4 to 6, the time T is T=43To+t ・・・・・・・−・・・・・・・・・
...(1) 60, and the output I of the numerical calculation circuit 72
= 40°50, 60.70.

Next, Table 7 shows the FFT input data addresses generated when bits are reversed in the vertical direction of the address space. Further, Table 8 shows FFT input Kadeka data addresses that occur when the transition time t is continuous and the bits are not reversed. All numbers in Tables 7 and 8 are in octal numbers except for the time.

Regarding Tables 7 and 8, [Time T is T=16T, +t+192...
The relationship is as shown in (2). and T□=0.1,2. reactor,
When taking the value of 4,5°6.7, the output R of the numerical calculation circuit 72 is 0.1, 2, 3, 4.5, 6.7, and the output I of the numerical calculation circuit 72 is 40.41, 42, 43, 44
, 45°46.47.

Here, the output format of the main blocks of the FFT address generator according to the present invention will be explained. Figure 9 (a
) is a case where the lower 6 bits in the horizontal direction of the address space are bit reversed (bit reverse access), and the focus is reversed by selecting the output of the numerical calculation circuit 76 inputted via the bit reverse bus 74 by the selector 75. be done. At this time, in the output of the selector 75, the top 6
However, by shifting with the barrel shifter 76, it can be taken out as the lower 6 pins. Further, (b) in the same figure shows a case where bit reversal is not performed (a case where bit reverse order access is not performed), and the numerical calculation circuit 73
The output of the barrel shifter 76 becomes equal to the output of the barrel shifter 76.

Next, FIG. 10(a) shows the case where the lower two bits in the vertical direction of the address space are bit reversed, and the address space shown in FIG. 9(a)
As in the case of , the output of the selector 75 is the upper 2 bits, but the required data can be extracted by shifting y with the barrel shifter 76 (see Fig. 10(a)).
), it is shifted to the center, but this means that the output of the barrel shifter 76 is 10.20.3 as shown in Tables 7 and 8.
This is because it takes a value of 0). Further, (b) of the same figure shows the case where bit inversion is not performed, and the bits are shifted to the center as in the case of (a).

In this way, the FFT address generator of the present invention can be used to perform the bit reversal access required for the radix-2 time-decimated FFT algorithm.

Furthermore, since the time decimation FFT algorithm and the frequency decimation algorithm differ only in whether bit reversal is performed first or last, the FFT algorithm generator according to the present invention can be used not only for the time decimation FFT algorithm but also for the time decimation FFT algorithm. , the bit-reverse order access required for the frequency a decimation algorithm can also be easily performed.

Although the embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to the above-mentioned embodiments, and can be modified as appropriate within the scope of the gist of the present invention. For example, in the above embodiment, the case of 8 bits was explained, but the bit reversal access required for the radix 2 time decimation 9 frequency decimation F'FT algorithm at an arbitrary number of bits (=2n points) is not limited to this. can be carried out.

〔Effect of the invention〕

As explained above, according to the FFT address generator according to the present invention, necessary data can be extracted in one cycle by directly bit-inverting the output of the numerical arithmetic circuit and then shifting the required number of bits using the barrel shifter. Therefore, it is possible to provide an FF'T address generation device that can perform bit inversion access at high speed, compared to the conventional method of inverting bits by shifting bits one by one, for example.

In addition, specifying whether or not bits are to be reversed in the address space and the number of shifts by the barrel shifter at that time can be performed by switching between two types of modes (the action of the bit reversal bus and the selector, and the action of the barrel shifter). It's extremely easy.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram showing the backfly operation in l''F T, and Figure 2 is the time thinning albo dimension Fl in FFT.
! Figure 5 is an explanatory diagram showing the arrangement of calculation data of ゛T. Figure 5 is an explanatory diagram showing focus reversal with different number of points. Figure 6 is an explanatory diagram showing bit reversal of two-dimensional 1" FT. Figure 7 is FIG. 8 is a block diagram showing the I"li" T address generator according to the present invention, and FIG. 9 is a block diagram for explaining the bit reverse order bus of the FFT address generator of FIG.
) and (b) and FIGS. 10(a) and (b) are explanatory diagrams showing the output format in the main blocks of the OFF'T address generator of FIG. 7. 72... first calculation means (numerical calculation circuit), 73...
・Second calculation means (numerical calculation circuit), 74...Bit reversal bus, 75...Selector, 76...
- Barrel shifter, 77... addition means (adder). C Figure 2 Figure 3 FFT foot P limb
Do'-) Pig Roller/1Y Customer Figure 6□□Outside□ Possible 3 Do5 6 Funeral Figure 8

Claims (1)

[Claims] The first device has at least a register function and a numerical calculation function. a second calculation means, a selector for bit-reversing the output of the second calculation means, a barrel shifter for shifting the output of the selector, and an increase in the output of the first calculation means and the output of the barrel chic. and an addition means for
FFT address generator with patented ability to perform bit reversal high-speed access