JPS59218049A - Channel selecting device - Google Patents

Channel selecting device

Info

Publication number
JPS59218049A
JPS59218049A JP58137042A JP13704283A JPS59218049A JP S59218049 A JPS59218049 A JP S59218049A JP 58137042 A JP58137042 A JP 58137042A JP 13704283 A JP13704283 A JP 13704283A JP S59218049 A JPS59218049 A JP S59218049A
Authority
JP
Japan
Prior art keywords
frequency
division ratio
frequency division
programmable
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58137042A
Other languages
Japanese (ja)
Inventor
Tatsuo Yugawa
湯川 達雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58137042A priority Critical patent/JPS59218049A/en
Publication of JPS59218049A publication Critical patent/JPS59218049A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03JTUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J7/00Automatic frequency control; Automatic scanning over a band of frequencies
    • H03J7/02Automatic frequency control
    • H03J7/04Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant
    • H03J7/06Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant using counters or frequency dividers
    • H03J7/065Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant using counters or frequency dividers the counter or frequency divider being used in a phase locked loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/193Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider

Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

PURPOSE:To attain easily an economical fine adjustment by using a PLL circuit of a pulse swallow system and obtaining fine adjustment data for adjusting finely a tuning frequency. CONSTITUTION:A programmable frequency divider 2 of the PLL consists of a swallow counter 9 and a programmable counter 8. Further, a 2-modulus prescaler 11 whose output is given to the programmable frequency divider 2 and to which an output of the counter 9 is fed back is provided and a control section 12 is connected to the frequency divider 2. The control section 12 forms data adjusting finely the receiving frequency. An automatic fine adjusting signal is supplied to a comparator 13 and its output is fed to a controller 14 together with a manual fine adjusting signal. The controller 14 generates the fine adjusting data signal and its signal is stored in an RAM15. An output of the controller 14 is stored temporarily in a register 16. The content of the register 16 is decentralized and connected to two counters in the PLL loop.

Description

【発明の詳細な説明】 本発明は、例えばテレビジョン受体機に用いられる選局
装置に関し、特に受信周波数の微調整に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel selection device used, for example, in a television receiver, and particularly to fine adjustment of a receiving frequency.

近年、テレビジョンの選局装置等にフェーズロックドル
ープ(以下1− PLL J (Pilase Loc
kedLoop )という。)シンセサイザ一方式が採
用されている。
In recent years, phase-locked loops (hereinafter referred to as 1-PLL J) have been used in television channel selection devices, etc.
kedLoop). ) One type of synthesizer is used.

このPLLにおいては、動作範囲を広げるため第1図に
示すような固定分周方式の構成が用いられている。すな
わち、PLLにおいて、電圧制御発振器1(以下1’−
VCOJという。)の発振周波数が高くなfi、TTL
+MO8で構成されるプログラマブル・デバイダ2の動
作範囲を越えると、PPLは正しい動作をしなくなる。
In this PLL, a fixed frequency division system configuration as shown in FIG. 1 is used in order to widen the operating range. That is, in the PLL, the voltage controlled oscillator 1 (hereinafter 1'-
It's called VCOJ. ) has a high oscillation frequency fi, TTL
If the operating range of the programmable divider 2 consisting of +MO8 is exceeded, the PPL will not operate correctly.

このため、プログラマブル・デバイダ2の前段に、グリ
スケ−23を置き、プログラマブル・デバイダ2への入
力周波数を下げる固定分周が行われる。
For this reason, a Grisscale 23 is placed before the programmable divider 2, and fixed frequency division is performed to lower the input frequency to the programmable divider 2.

第1図で、4はり7アレシス周波数発生器、5は位相比
較回路であり、その比較値はチャージポンプ6に入力さ
れ、このチャージポンフロの出力は、低域フィルタ7を
介してVCOIに入力されている。
In Fig. 1, 4 is a 7-alesis frequency generator, 5 is a phase comparison circuit, the comparison value is input to a charge pump 6, and the output of this charge pump flow is input to the VCOI via a low-pass filter 7. has been done.

ここで、VCOIの発振周波数=if。SC%’Jファ
レンス周波数発生器4のリファレンス周波数を’rlプ
リスケーラ30分周比をP1プログラマブル・デバイダ
2の分周比をNとすると、 fosc = P−N−f となる。したがって、分周比Nを変化させることにより
、受信したい放送局の局部発振周波数がVCOIから得
られる。
Here, the oscillation frequency of the VCOI=if. SC%'J The reference frequency of the reference frequency generator 4 is 'rl, the prescaler 30, the frequency division ratio is P1, and the frequency division ratio of the programmable divider 2 is N, then fosc=P-N-f. Therefore, by changing the frequency division ratio N, the local oscillation frequency of the broadcast station to be received can be obtained from the VCOI.

ところで、放送局からの送信周波数は予め定められてい
るが、実際は送信周波数は定められた周波数と正確に一
致していない場合が多い。そこで、TV上セツト側で微
調整を行なって最適回訓点にVCOの発振周波数f。S
Cを調整している。このためには、分周器20分周比を
こまかく、施えば1つづつ変化させている。今、プログ
ラマブル・デバイダ2の分周比Nを1だけずらしたとき
のf。SCのダ化分Δfoscは、 Δfosc ” P ・(N+1) −f、−P−N−
f。
Incidentally, although the transmission frequency from a broadcast station is determined in advance, in reality, the transmission frequency often does not exactly match the determined frequency. Therefore, fine adjustment is made on the TV set side to set the VCO oscillation frequency f to the optimum training point. S
Adjusting C. To this end, the frequency division ratio of the frequency divider 20 is changed minutely, perhaps one at a time. Now, f when the frequency division ratio N of programmable divider 2 is shifted by 1. The difference Δfosc of SC is Δfosc ” P ・(N+1) −f, −P−N−
f.

P−fr となる。したがって、プログラマブル・デバイダ2の分
周比N ’& ’1だけ変化させたときの発振周波数f
。SCは、リファレンス周波数f、をグリスケーラの分
周比に相当するP倍した値だけ変化することになる。こ
のΔfoBcが、微調の[:賃の1ステツプとなる。す
なわち、ステップがあらくなシ受信周波数の最適同調点
への微調が行えない欠点を有する。例えば、テレビジ目
ンにこの方式を用いた場合には、プリスケーラ3の分周
比を256、リファレンス周波数をl持上とすると、微
調可能なlステップは256IΦ2となってしまい、現
実には大きすぎる。
It becomes P-fr. Therefore, the oscillation frequency f when changing the division ratio of programmable divider 2 by N'&'1
. SC changes by a value obtained by multiplying the reference frequency f by P, which corresponds to the frequency division ratio of the grease scaler. This ΔfoBc becomes one step of the fine adjustment. That is, it has the disadvantage that the steps are rough and fine tuning to the optimum tuning point of the receiving frequency cannot be performed. For example, when this method is used for television, if the division ratio of the prescaler 3 is 256 and the reference frequency is increased by l, the l step that can be finely adjusted becomes 256IΦ2, which is too large in reality. .

リファレンス周波数発生器の分周比をプログラマブルに
して、微調を行う方式も知られている。
A method is also known in which the frequency division ratio of the reference frequency generator is made programmable for fine adjustment.

しかし、この方式は、受信周波数によって周波数分解能
が異なるとともに、リフアレシス周波数発生器が高価に
なる欠点がある。
However, this method has the disadvantage that the frequency resolution differs depending on the receiving frequency and that the reflex frequency generator is expensive.

本発明は、lステップの可変周波数が小さく、動作が安
定であって、経済的な微F1.1整を容易に行うことが
できる選局装置を提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a channel selection device that has a small variable frequency in l steps, is stable in operation, and can easily perform economical fine F1.1 adjustment.

本発明は、PLL回路にパルス・スワロ一方式を採用し
、微調整を可能にすることに着目したものである。すな
わち、本発明は、パルス・スワロ一方式のPLL回路を
用い、同調周波数の微調整を行なうだめの微調整データ
を得、このデータに基づいてパルス・スワロ一方式に用
いられるスワロ−カウンタのデータから先に変化させて
分周比を変更させることを特徴とする。
The present invention focuses on employing a pulse/swallow type in the PLL circuit to enable fine adjustment. That is, the present invention uses a pulse/swallow type PLL circuit to obtain fine adjustment data for finely adjusting the tuning frequency, and based on this data, swallow counter data used in the pulse/swallow type is adjusted. The feature is that the frequency division ratio is changed by changing the frequency division ratio first.

本発明一実施例を図面に基づいて説明する。第2図は、
本発明一実施例構成図である。第1図で説明した従来例
構成と比較すると、PT、Lのプログラマブル分周器が
スワロ−カウンタ9とプログラマブルカウンタ8とで構
成されており、プログラマブル分周比2にその出力が接
続され上記スワロ−カウンタ9の出力が帰還される2モ
ジラス・グリスケーラ11を含み、゛このプログラマブ
ルデバイダ2に制御部12が接続されたところに% t
Dがある。分周器2への分周比の設定は、スワロ−カウ
ンタ9とプログラマブルカウンタ8とに分けて設定され
、スワロ−カウンタ9の方に分周比の下位データがセッ
トされる。プリスケーラ11は二つの分周比をもち、ス
ワロ−カウンタ9の出力によシ、どちらか一方の分周比
でVCOlからの信号を分周する。
An embodiment of the present invention will be described based on the drawings. Figure 2 shows
FIG. 1 is a configuration diagram of an embodiment of the present invention. Compared to the conventional configuration explained in FIG. - includes a 2-modulus scaler 11 to which the output of the counter 9 is fed back;
There is a D. The frequency division ratio for the frequency divider 2 is set separately for the swallow counter 9 and the programmable counter 8, and the lower data of the frequency division ratio is set for the swallow counter 9. The prescaler 11 has two frequency division ratios, and divides the signal from the VCO1 by one of the frequency division ratios depending on the output of the swallow counter 9.

制御部12は、受信周波数を微調整するためのデータを
つくる。この微調用データは選局装置自体が検波出力等
を利用してつくる自動微調整信号とセットの外部からの
人の操作によりつくられる手動微調整信号とから得られ
る。自動微調整信号はコンパレータ13に供給される。
The control unit 12 creates data for finely adjusting the reception frequency. This fine adjustment data is obtained from an automatic fine adjustment signal created by the tuning device itself using the detection output, etc., and a manual fine adjustment signal created by a person operating from outside the set. The automatic fine adjustment signal is supplied to a comparator 13.

このコンパレータ13の出力は手動微調信号と共に制御
装置14に供給される。制御装w14は微調データ信号
を発生し、その信号は、微調のステップ幅および方向と
してRAM(ランダムアクセスメモリ)15に記憶・さ
れる。制御装置14の出力はレジスタ16に一時記憶さ
れる。制御装ffi+4は、上述の微調データと共に、
所定の放送局を受信するためにその放送局に対応した分
周比も発生する。したがって、レジスタ16の内容は、
結合回路IOにより、PLLのループ内に含まれる2個
のカウンタに分配して接続される。すなわち、レジスタ
16の下位データはスワロ−カウンタ9に、レジスタ1
6の上位データはプログラマブルカウンタ8にそれぞれ
結合される。この制御部12が微調整の制御のみに使用
される場合には、結合回路lOはレジスタ16の下位桁
をスワロ−カウンタ9に与える回路のみを含み、上位桁
をプログラマブルカウンタ8に与える回路を省いてもよ
い。
The output of this comparator 13 is supplied to a control device 14 together with a manual fine adjustment signal. The control unit w14 generates a fine adjustment data signal which is stored in a RAM (Random Access Memory) 15 as the fine adjustment step width and direction. The output of the controller 14 is temporarily stored in a register 16. The control device ffi+4, together with the above-mentioned fine adjustment data,
In order to receive a predetermined broadcast station, a frequency division ratio corresponding to the broadcast station is also generated. Therefore, the contents of register 16 are:
The coupling circuit IO distributes and connects the two counters included in the PLL loop. That is, the lower data of register 16 is sent to swallow counter 9, and the lower data of register 16 is sent to swallow counter 9.
The upper data of 6 is coupled to a programmable counter 8, respectively. When this control section 12 is used only for fine adjustment control, the coupling circuit 10 includes only a circuit that supplies the lower digits of the register 16 to the swallow counter 9, and omit the circuit that supplies the upper digits to the programmable counter 8. You can stay there.

その他の構成については、第1図で説明した従来例構成
と同様であるので説明の繰返しを省く。
The rest of the configuration is the same as the conventional configuration explained in FIG. 1, so the explanation will not be repeated.

このような構成では、2モジラス・グリスケ−211の
2個の分周比をPおよびP+1.スワロ−カウンタ9の
プリセット値を”Is プログラマブルカウンタ8のプ
リセット値をNp とすると、VCOIの発振周波数f
。scは fosc ” t (Np−n、 ) ・P+nt (
P+1)’)’rとなる。
In such a configuration, the two frequency division ratios of the 2-modulus Griskey 211 are P and P+1. If the preset value of the swallow counter 9 is "Is" and the preset value of the programmable counter 8 is Np, then the oscillation frequency f of the VCOI is
. sc is fosc ” t (Np-n, ) ・P+nt (
P+1)')'r.

ただし、プログラマブルデバイダ2の分周比Nは、 N = PNp 十〇。However, the frequency division ratio N of programmable divider 2 is N = PNp 10.

となる。ここで、”1は分周比の下位データ、Npはそ
の上位データをそれぞれを示す。したがって、スワロ−
カウンタ9を1つ計数して、Nilだけ変化させるとき
、fQf3Cの変化分ΔfO8cは、Δ’osc”((
NP−(n++1))P+(nt+1)(P+1)) 
fr−((N P−nt) P+nt (P+ 1 )
 )fr= (−P+(P+1 ) ) f。
becomes. Here, "1" indicates the lower data of the frequency division ratio, and Np indicates its upper data. Therefore, the swallow
When the counter 9 counts one and changes by Nil, the change ΔfO8c in fQf3C is Δ'osc"((
NP-(n++1))P+(nt+1)(P+1))
fr-((NP-nt) P+nt (P+ 1)
) fr= (-P+(P+1)) f.

=f。=f.

セなり、リファレンス周波数の値に一致する。つまり、
第1図に示した従来例構成のPLLに比較して、グリス
ケーラ3(第1図)に関係なく細かい微調整が可能とな
る。
and matches the value of the reference frequency. In other words,
Compared to the PLL having the conventional configuration shown in FIG. 1, detailed fine adjustment is possible regardless of the grease scaler 3 (FIG. 1).

次に動作を説明すると、受信したい放送局に対応した分
周比データが制御装置14からレジスタ16f:介して
分周器2のスワロ−カウンタ9およびプログラマプルカ
ウンタ8ヘセツトされる。これによって、VCOIの発
振周波17f。8cは、受信したい放送局に対応した局
部発振周波数が得られるようにPLL回路によって制御
され、その結果、受信状態となる。ところが、受信周波
数と同調周波数とがすれていることが検出されると、そ
のずれが自動微調信号としてコンパレータ13に与えら
れる。この自動微調信号は、コンパレータ13により基
準電圧と比較され、この比較値が制御回路14に入力さ
れる。制御装置14は、内蔵されたゾログラムの処理に
従って微調の方向< ’oscを増加または減少するこ
と)を定め、レジスタJ6を介して分周比Nの下位デー
タを示すスワロ−カウンタ9から1つづつ正または狛に
計数し1分周比Nを1つづつ変化させる。それに従って
、VCOlのf。SCは基準周波数frを1ステツプと
して変化していく。同調がとれた時点でこの微調制御1
141動作は終了する。再度同調がずれれば、再度上記
動作が行われ、常に正しい同調が取られる。まだ、手動
微調整の場合には、制御装置14に、手動微調信号を入
力し、同様な制御を行う。
Next, the operation will be described. Frequency division ratio data corresponding to a broadcast station desired to be received is set from the control device 14 to the swallow counter 9 and programmable counter 8 of the frequency divider 2 via the register 16f. As a result, the oscillation frequency of the VCOI is 17f. 8c is controlled by a PLL circuit so as to obtain a local oscillation frequency corresponding to the broadcast station to be received, and as a result, becomes in a receiving state. However, if it is detected that the receiving frequency and the tuning frequency are out of alignment, the deviation is provided to the comparator 13 as an automatic fine adjustment signal. This automatic fine adjustment signal is compared with a reference voltage by a comparator 13, and this comparison value is input to a control circuit 14. The control device 14 determines the direction of fine adjustment (increase or decrease osc) according to the processing of the built-in zologram, and inputs one by one from the swallow counter 9 indicating the lower data of the frequency division ratio N via the register J6. The frequency division ratio N is changed one by one by counting positively or squarely. Accordingly, f of VCOl. SC changes with reference frequency fr in one step. When synchronization is achieved, this fine adjustment control 1
141 operation ends. If the tuning goes out again, the above operation is performed again, and correct tuning is always achieved. In the case of manual fine adjustment, a manual fine adjustment signal is input to the control device 14 to perform similar control.

これら微調制御の際に、微調整のステップ数と方向とを
RAM15に記憶させることによって、微調の度合を保
持することがよい。例えば、I?、AM15の1ビツト
を1ステツプとし、@調制御の度に記憶内容を1つづつ
インクリメントまだはデクリメントさせる。また、微調
整の方向を決定するためRAM15の別の1ビツトを使
用することがよい。
During these fine adjustment controls, it is preferable to maintain the degree of fine adjustment by storing the number and direction of fine adjustment steps in the RAM 15. For example, I? , AM15 is taken as one step, and the stored contents are incremented or decremented by one each time the @ key control is performed. It is also preferable to use another bit in RAM 15 to determine the direction of fine adjustment.

以上説明したように本発明によれば、従来のPLLに分
周比の変化によるVCOの発振周波数変化分がリファレ
ンス周波数に一致させることができる付加回路を設け、
さらに同調周波数のずれに応じて分周比を1つづつ増加
または減少させる制御部を設けたので、受信周波数の細
かい微調を行うことができる。この回路はPLL回路の
特質により安定であるとともに、回路構成が簡単であっ
て経済的である。また、周波数毎に変化分が相違するこ
ともないので、@調整ステップが選択周波数によシ均一
になる。したがって、本発明によれば、安定した微調整
が行ない得る選局装置を提供できる。
As explained above, according to the present invention, the conventional PLL is provided with an additional circuit that can make the change in the oscillation frequency of the VCO due to the change in the frequency division ratio match the reference frequency,
Further, since a control section is provided that increases or decreases the frequency division ratio one by one in accordance with the shift in the tuning frequency, fine tuning of the reception frequency can be performed. This circuit is stable due to the characteristics of a PLL circuit, and has a simple circuit configuration, making it economical. Further, since the amount of change does not differ for each frequency, the @adjustment step becomes uniform depending on the selected frequency. Therefore, according to the present invention, it is possible to provide a channel selection device that can perform stable fine adjustment.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例を示す構成図、第2図は本発明の一実施
例を示す構成図である。 1・・・・・・電圧制御発振器、2・・・・・・プログ
ラマブル・デバイダ、3・・・・・・グリスケーラ、4
・・・・・・す7アレンス周波数発生器、訃・・・・・
位相比較回路、6・・・・・・チャージポンプ、7・・
・・・・低域フィルタ、8・旧・・スワロ−カウンタ、
9・−・・・・プログラマブルカウンタ、10・・・・
・・結合回路、11・・・−・・2モジラス・プリスケ
ーラ、12・・・・・・制御部、13・・・・・・コン
パレータ% 14・・・・・・制御装置、15・・・・
・・几AM、16・・・・・・レジスタ。 ! 寿1図 嘉Z 図
FIG. 1 is a block diagram showing a conventional example, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1...Voltage controlled oscillator, 2...Programmable divider, 3...Grise scaler, 4
・・・・・・7 Allens frequency generator, death...
Phase comparison circuit, 6...Charge pump, 7...
...Low pass filter, 8.Old...Swallow counter,
9...Programmable counter, 10...
...Coupling circuit, 11...-2 modulus prescaler, 12...Control unit, 13...Comparator% 14...Control device, 15...・
・・几AM、16・・・・・・Register. ! Kotobuki 1 diagram Kaz diagram

Claims (1)

【特許請求の範囲】[Claims] 電圧制御発振器の出力信号を第1の分周比又は第2の分
周比で分周して出力するグリスケーラと該グリスケーラ
の出力信号を設定された分周比で分周して出力するプロ
グラマブル分周器とを有し、該プログラマブル分周器を
スワロ−カウンタおよびプログラマブルカウンタで構成
して前記プログラマブル分周器に設定すべき分周比を該
スワロ−カウンタと該プログラマブルカウンタとに分け
て設定し、前記スワロ−カウンタの出力により前記グリ
スケーラの分周比が前記第1の分周比又は前記第2の分
周比となるように制御するパルススワロ一方式のフェー
ズ・ロックド・ループ回路を備えることにより、前記プ
ログラマブル分周器に設定された分周比に対応した放送
局を受信する選局装置において、同調周波数の微調整を
行なうだめの微調整データを得る手段と、該微調整デー
タに基づいて前記スワロ−カウンタに設定されている分
周比データから先に変化させることにより前・記プログ
ラマブル分周器に設定されている分周比を変更する手段
とが設けられていること全特徴とする選局装置。
A grease scaler that divides the output signal of the voltage controlled oscillator by a first frequency division ratio or a second frequency division ratio and outputs the result, and a programmable divider that divides the output signal of the grease scaler by a set frequency division ratio and outputs the result. a frequency divider, the programmable frequency divider is configured with a swallow counter and a programmable counter, and a frequency division ratio to be set in the programmable frequency divider is set separately for the swallow counter and the programmable counter. , by comprising a pulse swallow one-type phase-locked loop circuit that controls the frequency division ratio of the grease scaler to be the first frequency division ratio or the second frequency division ratio based on the output of the swallow counter. , in a tuning device for receiving a broadcasting station corresponding to a frequency division ratio set in the programmable frequency divider, means for obtaining fine adjustment data for finely adjusting a tuning frequency; All features include means for changing the frequency division ratio set in the programmable frequency divider by first changing the frequency division ratio data set in the swallow counter. Channel selection device.
JP58137042A 1983-07-27 1983-07-27 Channel selecting device Pending JPS59218049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58137042A JPS59218049A (en) 1983-07-27 1983-07-27 Channel selecting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58137042A JPS59218049A (en) 1983-07-27 1983-07-27 Channel selecting device

Publications (1)

Publication Number Publication Date
JPS59218049A true JPS59218049A (en) 1984-12-08

Family

ID=15189501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58137042A Pending JPS59218049A (en) 1983-07-27 1983-07-27 Channel selecting device

Country Status (1)

Country Link
JP (1) JPS59218049A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04506592A (en) * 1989-06-29 1992-11-12 モトローラ・インコーポレーテッド Frequency synthesizer with interface controller and buffer memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04506592A (en) * 1989-06-29 1992-11-12 モトローラ・インコーポレーテッド Frequency synthesizer with interface controller and buffer memory

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