JP3322331B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit for use in digital video signal processing such as television video display on a PDP, which locks stably even if an input reference signal fluctuates.

[0002]

BACKGROUND ART In a PLL circuit including a varying clock generator output frequency by writing parameters to determine the conventional oscillation frequency <br/> in the loop, the parameter
And the value of the frequency range that the PLL circuit can lock using
Multiple parameters can be locked by associating them with parameters
Stores a parameter table arranged in the order of possible frequency values
Storage means for performing the operation. In addition, with each parameter
The lockable frequency range depends on a parameter and
Some frequency ranges are over due to the parameters listed.
-It is decided to wrap. And entered
Clock signal output with the reference signal
Phase deviation from the output frequency of the
In the case above, search the parameter table and find this phase
The direction of the frequency to correct the deviation and the value of the corresponding frequency range
The parameter next to the current parameter.
Was written to the clock generator. In this case, since the extracted parameters operate near the end of the frequency range in which the extracted parameters can be locked and output, if the cycle of the input reference signal fluctuates due to, for example, switching of the input video signal, the lock is often released, and unstable. Becomes

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has been developed in view of the above problem.
L.

[0004]

Means for detecting a phase shift of a predetermined value or more between an input reference signal and a feedback signal, means for calculating the frequency of occurrence of the phase shift, and oscillation frequency
A clock generator division ratio by the write parameter has been inserted into the loop of the PLL circuit changes to determine the wave number, and a control means for writing the clock generator calculates a parameter by said phase shift, said para
A frequency range in which the PLL circuit can be locked using a meter.
A plurality of the parameters are associated with each other by associating the values of the boxes with the parameters.
Parameters in which parameters are arranged in order of lockable frequency
Storage means for storing a data table, when the frequency of occurrence of the phase shift is equal to or greater than a predetermined value, it is possible to output a frequency within a frequency range in which the current parameter can be locked and output, and Phase to correct phase shift
Change parameters, which are multiple parameters corresponding to the wave number direction
Select the parameter located at the center from the meter group.
To the clock generator.

There is an odd number of the change parameter groups.
In the case, the changed parameter group not including the current parameter
The parameter located at the center is selected from the above and written into the clock generator.

Further, there is an even number of the change parameter groups.
In the case, the current parameter and the changed parameter group
A parameter located at the center from the middle is selected and written to the clock generator.

[0007] The phase shift detecting means may include the input base.
When higher than the constant voltage output voltage of the low-pass filter for integrating the output of the phase comparator for comparing the phase of the quasi-signal and the feedback signal is predetermined is provided a comparator circuit which outputs a logic 1, the output signal of the comparator circuit Is a phase delay signal or a phase advance signal.

[0008] Further , the means for detecting the phase shift is provided by the input base.
The output voltage of the low-pass filter for integrating the output of the phase comparator for comparing the phase of the quasi-signal and the feedback signal is predetermined.
A comparison circuit that outputs a logic 1 when the voltage is lower than the predetermined voltage, and an output signal of the comparison circuit is a phase advance signal or a phase delay signal.

[0010]

A means for detecting a phase shift of a predetermined value or more between an input reference signal and a feedback signal, a means for calculating the frequency of occurrence of the phase shift, and a parameter for determining an oscillation frequency
A clock generator which is inserted into the loop of the PLL circuit which changes its frequency dividing ratio by writing over data, and a control means for writing the clock generator calculates a parameter by said phase shift, said using said parameter P
The value of the frequency range in which the LL circuit can lock and the parameter
Multiple parameters can be locked by linking to parameters
Memorize the parameter table arranged in order of various frequency values
When the occurrence frequency of the phase shift is equal to or more than a predetermined value, a frequency within a frequency range in which the current parameter can be locked and output can be output.
And corresponding to the direction of the frequency for correcting the phase shift.
From the group of change parameters that are multiple parameters,
By selecting a parameter located at the center and writing it to the clock generator, a parameter having a frequency to be locked and output at substantially the center can be set in the clock generator, and the clock generator can be stably locked.

When there are an odd number of the change parameter groups
Is the change parameter group that does not include the current parameter.
By selecting the parameter located in the center from and writing to the clock generator, each parameter is an odd number
In some cases, the parameters can be easily selected .

When there is an even number of the change parameter groups
Is the current parameter and the changed parameter group
By selecting a parameter located at the center from the above and writing it to the clock generator, the parameter can be easily selected even when there are even numbers of parameters.

[0013] The phase shift detecting means is provided with the input reference signal.
A comparison circuit output voltage of the low-pass filter to output a logical 1 is higher than a predetermined constant voltage for integrating the output of the phase comparator for comparing the phase of said feedback signal provided and, the
By using the output signal of the comparison circuit as a phase delay signal or a phase advance signal, it is possible to reliably detect the phase delay or the phase advance.

[0014] The phase shift detecting means is provided with the input reference signal.
The output voltage of the low-pass filter that integrates the output of the phase comparator that compares the phase of the feedback signal with the feedback signal is a predetermined constant value.
Provided a comparison circuit for outputting a logical 1 is lower than the voltage, the
By using the output signal of the comparison circuit as a phase advance signal or a phase delay signal, it is possible to reliably detect the phase advance or the phase delay.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a PLL circuit according to the present invention will be described in detail with reference to the drawings. FIG. 1 shows a PLL according to the present invention.
FIG. 3 is a block diagram of one embodiment of a circuit. The phase of the input reference signal S1 such as a horizontal synchronization signal and the feedback signal S2 of the PLL are compared by the phase comparator 1, and the duty pulse corresponding to the phase difference output from the phase comparator 1 is integrated by the LPF (low-pass filter) 2. controlling the VCO (voltage controlled Oscillator) 3 as a DC level signal by. The output of the VCO 3 is divided by the clock generator 4 and the counter 5 to obtain a feedback signal S2. Thus, the output signal S3 of the PLL circuit such as the clock signal of the video signal locked to the input reference signal S1 can be obtained. Here, the clock generator 4 has a parameter P which is written from outside and determines the oscillation frequency.
It has a function that can arbitrarily set the frequency division ratio depending on the value of X. The output of LPF 2 is sent to comparator 6 and comparator 7.
Each of them is input, and a predetermined constant voltage S5 is
A predetermined constant voltage S7 is supplied to the comparator 6,
Each has been entered. Furthermore, the output level of the comparator 6 is
The phase lag signal S6 and the phase advance signal S output from the comparator 7
8 is input to the MPU 8, and the MPU 8
Parameter PX is output to lock generator 4
You. The MPU 8 has a clock 8 necessary for the operation of the MPU 8.
b and the frequency of occurrence of the phase delay signal S6 and the phase advance signal S8
A phase shift calculator 8c for calculating the frequency, and a clock generator.
Using the parameter PX for writing to the
The value of the frequency range in which the LL circuit can lock and the parameter P
X can be associated with multiple parameters that can be locked.
Parameter table 8e stored in the order of wave number values
And a parameter based on the calculation result of the phase shift calculating unit 8c.
Parameter selection for selecting parameters from the data table 8e
And a constant section 8d.

FIG. 2 shows the parameters set in the clock generator and the frequency range in which the PLL circuit locks and outputs. Parameters to be set for clock generator 4
P1 to P9 which are the values of the parameters of the
The frequency that the PLL circuit can lock using the value of each parameter
Numerical ranges (ranges indicated by arrows) are shown. And this P
1 to P9 parameter values and their corresponding frequencies
The value in the numerical range is associated with the parameter table 8e.
It is remembered. For example, each parameter value P1, P2,.
・ Select an appropriate parameter such as P5 from among
When the frequency of the L output signal S3 is stably locked at F0 and the operation is performed, if the input reference signal S1 shifts to a higher frequency due to switching of the input signal source or the like, the frequency of the PLL output signal S3 becomes, for example, F2, and the lock is achieved. Coming off or hanging
As a result, the phase shifts frequently.

The phase shift is detected by comparing the output signal S4 of the LPF 2 with a predetermined constant voltage S5 by a comparator 6,
When the output signal S4 of the LPF 2 is higher than the fixed voltage S5, a phase delay signal S6 is output, usually as a phase delay. M
The occurrence frequency is calculated by counting the number of occurrences of the phase delay signal S6 within a certain time by the phase shift calculating unit 8c of the PU 8, and when the occurrence frequency exceeds a predetermined certain frequency, M
The PU 8 recognizes that the frequency range to be output stably is out of the range with the parameter P5, and the parameter selecting unit 8d selects a new parameter PX from the parameters stored in the parameter table 8e and sets it in the clock generator 4. For this reason, the parameter selecting unit 8d
Refer to the value of the frequency range of each parameter in Table 8e
Within the frequency range where the current parameter can be locked and output
Search for parameters that can output the frequency of
You. In this case, P5 is in the frequency range from F1 to F2.
Output a frequency within this frequency range.
The parameters that can be set are the parameters from P1 to P9.
Become Then, the parameter selecting unit 8d determines from P1 to P
9, the phase lag direction D2 (phase
The direction of the frequency to correct the deviation) and the corresponding parameter
Parameters having values in the frequency range within the table 8e
Is retrieved. For this reason,
The data selection unit 8d determines each parameter in the parameter table 8e.
Refer to the frequency range value of the
Output a higher frequency than the
Search for a pair that can be In this example, P5 is F
Since it has a frequency range of 1 to F2, the frequency of F2
Parameters that can output frequencies higher than the number
Is the parameter of P6 to P9 in the parameters of P1 to P9.
Parameters. That is, these parameters change
It becomes a parameter group. Further, the parameter selection unit 8d
Selects the parameter located in the center of the group of changed parameters.
Select. In this example, an even number of P6, P7, P8, P9
Current parameters P5 and P6, P
Change parameter group consisting of parameters 7, 7, P8 and P9
And the parameter located at the center, that is, P7
Select a parameter. Then, the MPU 8 determines that the P7
The parameters are written to the clock generator 4.

Also, for example, by selecting the parameter P5
The frequency of the PLL output signal S3 is stably locked at F0.
During operation, the input reference signal is changed by switching the input signal source, etc.
When the signal S1 shifts to a lower frequency, the output signal of the LPF2
S4 is compared with a predetermined constant voltage S7 by the comparator 7.
Therefore, the output signal S4 of the LPF 2 is lower than the constant voltage S7.
Lower than normal, the phase advance signal S8 is
Is output. The phase shift calculator 8C of the MPU 8 calculates this phase.
The occurrence frequency is calculated by counting the number of occurrences of the advance signal S8 within a certain time, and when the occurrence frequency exceeds a predetermined certain frequency, the MPU 8 recognizes that the frequency range is stably out of the parameter P5. The parameter selecting unit 8d selects a new parameter PX from the parameters stored in the parameter table 8e and sets it in the clock generator 4. It should be noted that a method of selecting a new parameter PX is such that the parameter selecting unit 8d sets the parameters P1 to P9.
From the parameters, this phase lead direction D1 (phase shift)
Lower frequency direction) and corresponding parameters
Parameters having values in the frequency range within the table 8e
The description is omitted because it is the same except that the change parameter group is searched. That is, the parameter selection unit 8d
Of the frequency range of each parameter in the parameter table 8e
By referring to the value, the frequency at which the current parameter can be locked and output
Parameter that can output a frequency lower than the wave number
Search for. For example, if the change parameter group is P2, P3, P
If the parameter is 4, the parameter selection unit 8
d is an odd number of parameters P2, P3, P4
Therefore, the parameter located in the center, that is, the parameter of P3
Parameters are selected and MPU 8
Write P3 to the clock generator 4.

[0020]

As described above, the frequency of occurrence of phase shift
If the degree is equal to or greater than a predetermined value, the current parameter
Output a frequency within the frequency range that can be output.
Parameters to correct the phase shift
The frequency range in the parameter table corresponding to the direction of the wave number
A change parameter group that is a plurality of parameters with enclosed values
Search for the parameter located at the center of the
Data to the clock generator.
By writing, it is possible to obtain an output signal that is stably locked and output even if the input reference frequency changes.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of a PLL circuit according to the present invention.

FIG. 2 is a diagram illustrating parameters set in a clock generator and a frequency range in which a PLL circuit locks and outputs.

[Explanation of symbols]

1 phase comparator 2 LPF (low pass filter) 3 VCO (voltage controlled Oscillator) 4 clock generator 5 counter 6 comparator 7 comparator 8 MPU 8b clock 8c phase shift calculation section 8d parameter selection unit 8e parameter table S1 input reference signal S2 feedback signal S3 PLL output signal S4 LPF output S5 constant voltage S6 phase delay signal S7 constant voltage S8 phase advance signal PX parameter signal P1 to P9 parameters F0, F1, F2 PLL output frequency D1 phase advance direction D2 phase delay direction

Claims (5)

(57) [Claims] 1. A means for detecting a phase shift between an input reference signal and a feedback signal, which is equal to or greater than a predetermined value, a means for calculating a frequency of occurrence of the phase shift, and an oscillation frequency are determined.
Parameters and clock generator division ratio by the writing has been inserted into the loop of the PLL circuit to change in a control means for writing by calculating a parameter to the clock generator by the phase shift, using the parameters
The value of the frequency range in which the PLL circuit can lock
Parameters and lock multiple parameters.
Parameter table in the order of possible frequency values
Storage means for storing , when the frequency of occurrence of the phase shift is equal to or more than a predetermined value, a frequency within a frequency range in which the current parameter can be locked and output can be output, and the phase shift can be output. In the direction of the frequency to correct
In the change parameter group corresponding to multiple parameters
Wherein a parameter located at the center is selected and written to the clock generator. 2. When there are an odd number of said change parameter groups
Is the change parameter group that does not include the current parameter.
2. The PLL circuit according to claim 1, wherein a parameter located at the center of the PLL circuit is selected and written to the clock generator. 3. A case where the number of change parameter groups is even.
Is the current parameter and the changed parameter group
2. The PLL circuit according to claim 1, wherein a parameter located at the center is selected and written to said clock generator. 4. A phase shift detecting means, comprising:
A comparison circuit that outputs a logic 1 when the output voltage of the low-pass filter that integrates the output of the phase comparator that compares the phase of the signal and the feedback signal is higher than a predetermined constant voltage;
4. The PLL circuit according to claim 1, wherein an output signal of the comparison circuit is a phase delay signal or a phase advance signal. 5. A phase shift detecting means, comprising:
One output voltage of the low-pass filter is determined Me pre for integrating the output of the phase comparator for comparing the phase of the No. and the feedback signal
A comparison circuit that outputs a logic 1 when the voltage is lower than the constant voltage is provided;
4. The PLL circuit according to claim 1, wherein an output signal of the comparison circuit is a phase advance signal or a phase delay signal.