JP3079809B2 - Phase comparison device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparator,
In particular, a counter separate from the program divider is provided, and the output signal (error out signal) from the phase comparison means is controlled by counting the input signal by the counter and comparing it with an expected value, thereby reducing the lock-up time. And a phase comparison device.

[0002]

2. Description of the Related Art Referring to FIG. 2 showing a block diagram of a conventional phase comparator, the phase comparator 200 includes a reference frequency generator 5 for producing a reference frequency, an input unit 4 for inputting a frequency to be measured, and A program divider 1 for dividing an output signal from the input unit 4, a division value setting register 2 for setting a division value to the program divider 1,
A phase comparator 3 which receives the output of the reference frequency generator 5 and the output of the program divider 1 as inputs,
Has a charge pump 6 that outputs a predetermined level according to the comparison result of

Next, the operation of the conventional phase comparator 200 will be described.

The input signal (f) to the program divider 1
in) is divided by the frequency division value (N) set by the frequency division value setting register 2 and the reference frequency signal (fref) from the reference frequency generator 5 is compared with the phase comparator 3
And the result indicates that fr from the charge pump 6
If ef> fin / N, a low level is output and fref <f
If in / N, a high level is output, and fref = fin / N
If so, a high impedance is output (see FIG. 4).

[0005] As shown in FIG.
After the high-frequency component is removed from the output 201 by the low-pass filter 12, the DC component is input to the VCO 13, and a frequency corresponding to the voltage level is output from the VCO 13. The output signal from the VCO 13 is input to the input unit 4 again, and the operation is repeated so as to gradually approach a predetermined frequency to lock the output 201.

[0006]

However, in this conventional phase comparator, a high impedance state exists between each of the high level and the low level output from the charge pump. There was a problem that the lock-up time was prolonged.

[0007]

According to the present invention, there is provided a phase comparison apparatus comprising: a reference frequency input means; a measured frequency input means;
Variable frequency dividing means for dividing the frequency to be measured, frequency dividing value setting means for setting a frequency dividing value to the variable frequency dividing means,
A phase comparison means for receiving the output of said variable frequency divider means and the output of the reference frequency input means, a first level output Output for outputting the high-level or low-level or high impedance state by the comparison result of the phase comparing means A phase comparison device comprising: a counting means for counting an output of the measured frequency input means for a predetermined period; an expected value storage means for storing an expected count value; and contents of the count means and the expected value storage means. And a result of the comparing means , wherein the result is the expected value.
If they do not match, exit the high or low state.
If the result matches the expected value,
And a second level output means for outputting the impedance state .

[0008]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a phase comparator according to a first embodiment of the present invention. The same components as those of the conventional phase comparison device are denoted by the same reference numerals.

The phase comparator 100 of this embodiment counts the frequency input from the input unit 4 by a counter 8 for a predetermined period, and matches the expected value preset in an expected value setting register 10 with a coincidence detection circuit 9. Compare with. A predetermined level (high level or low level) selected by the output selector 11 is output from the charge pump 6 'until a match is made according to the result of the match detection circuit 9, and when the match is made, the output is kept in a high impedance state. .

Next, a description will be given of a phase comparator according to a second embodiment of the present invention.

The phase comparison device 300 of the second embodiment
Has the same configuration as that of the first embodiment except that it has a mask register 14 for masking the lower bits of the expected value setting register 10 because the lock range actually has a width although it is said to lock to a predetermined frequency. Therefore, detailed description is omitted for illustration only (see FIG. 6).

As described above, the output 101 of the charge pump 6 output by the first and second embodiments and the charge pump
FIGS. 7 and 8 show application examples of the connection of the output 102 of 6 ' .

[0014]

As described above, according to the present invention, the output is controlled so that the high level or the low level is output until the frequency matches the predetermined frequency, and the output is set to the high impedance state when the frequency matches. This has the effect of shortening the lock-up time when the frequency is greatly changed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a phase comparison device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a conventional phase comparison device.

FIG. 3 is a circuit diagram of the phase comparator shown in FIG. 1;

FIG. 4 is a timing chart of the conventional example shown in FIG.

FIG. 5 is a block diagram of an application example of the conventional example shown in FIG. 2;

FIG. 6 is a block diagram of a phase comparison device according to a second embodiment of the present invention.

FIG. 7 is an application connection example of the output shown in FIG. 1;

FIG. 8 is another application connection example of the output shown in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Programmable divider 2 Dividing value setting register 3 Phase comparator 4 Input terminal 5 Reference frequency generator 6, 6 'Charge pump 8 Frequency counter 9 Match detection circuit 10 Expected value setting register 11 Selector 12 Low pass filter 13 VCO 14 Mask register 100 , 200, 300 Phase comparator 101, 102, 201 Charge pump output

Claims (1)

(57) [Claims] 1. A reference frequency input means, a measured frequency input means, a variable frequency dividing means for dividing the measured frequency, and a frequency dividing value setting for setting a frequency dividing value in the variable frequency dividing means. means, a phase comparator which receives the output of the output and the variable frequency divider means of the reference frequency input means, the first outputs a high-level or low-level or high impedance state by the comparison result of the phase comparing means In a phase comparison device including a level output output unit, a count unit that counts an output of the measured frequency input unit for a predetermined period, an expected value storage unit that stores an expected count value,
Comparing means for comparing the contents of the count means and the expected value storing means, and the result of the comparing means,
If does not match the expected value, the high or low level
Output a bell state, and the result matches the expected value.
And a second level output means for outputting a high impedance state .