JPS59215184A - バツフアメモリ制御方式 - Google Patents

バツフアメモリ制御方式

Info

Publication number
JPS59215184A
JPS59215184A JP58089073A JP8907383A JPS59215184A JP S59215184 A JPS59215184 A JP S59215184A JP 58089073 A JP58089073 A JP 58089073A JP 8907383 A JP8907383 A JP 8907383A JP S59215184 A JPS59215184 A JP S59215184A
Authority
JP
Japan
Prior art keywords
buffer memory
encoding
lines
circuit
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58089073A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0151117B2 (enrdf_load_html_response
Inventor
Hideo Kuroda
英夫 黒田
Naoki Takegawa
直樹 武川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP58089073A priority Critical patent/JPS59215184A/ja
Publication of JPS59215184A publication Critical patent/JPS59215184A/ja
Publication of JPH0151117B2 publication Critical patent/JPH0151117B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
JP58089073A 1983-05-23 1983-05-23 バツフアメモリ制御方式 Granted JPS59215184A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58089073A JPS59215184A (ja) 1983-05-23 1983-05-23 バツフアメモリ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58089073A JPS59215184A (ja) 1983-05-23 1983-05-23 バツフアメモリ制御方式

Publications (2)

Publication Number Publication Date
JPS59215184A true JPS59215184A (ja) 1984-12-05
JPH0151117B2 JPH0151117B2 (enrdf_load_html_response) 1989-11-01

Family

ID=13960672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58089073A Granted JPS59215184A (ja) 1983-05-23 1983-05-23 バツフアメモリ制御方式

Country Status (1)

Country Link
JP (1) JPS59215184A (enrdf_load_html_response)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61148987A (ja) * 1984-12-24 1986-07-07 Hitachi Ltd フレ−ム間符号化モ−ド制御方式
JPS63269883A (ja) * 1987-04-28 1988-11-08 Matsushita Electric Ind Co Ltd 準可変長符号ｄｐｃｍ符号化装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61148987A (ja) * 1984-12-24 1986-07-07 Hitachi Ltd フレ−ム間符号化モ−ド制御方式
JPS63269883A (ja) * 1987-04-28 1988-11-08 Matsushita Electric Ind Co Ltd 準可変長符号ｄｐｃｍ符号化装置

Also Published As

Publication number Publication date
JPH0151117B2 (enrdf_load_html_response) 1989-11-01

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