JPS59213168A - Manufacture of vertical type field effect transistor - Google Patents
Manufacture of vertical type field effect transistorInfo
- Publication number
- JPS59213168A JPS59213168A JP58088002A JP8800283A JPS59213168A JP S59213168 A JPS59213168 A JP S59213168A JP 58088002 A JP58088002 A JP 58088002A JP 8800283 A JP8800283 A JP 8800283A JP S59213168 A JPS59213168 A JP S59213168A
- Authority
- JP
- Japan
- Prior art keywords
- impurity region
- conductivity type
- region
- substrate
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 4
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000012535 impurity Substances 0.000 claims abstract description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 239000012212 insulator Substances 0.000 claims 2
- 238000009792 diffusion process Methods 0.000 abstract description 16
- 239000000758 substrate Substances 0.000 abstract description 15
- 238000000034 method Methods 0.000 abstract description 5
- 238000000992 sputter etching Methods 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract 5
- 238000005468 ion implantation Methods 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66719—With a step of forming an insulating sidewall spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
Description
【発明の詳細な説明】
本発明はＰ−Ｎ成金部金具える縦型ＭＯ８電界効果トラ
ンジスタの電気的％註の同上に関Ｔるものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the electrical characteristics of a vertical MO8 field effect transistor having a P-N metallization.
従来、プレーナ型縦型ＭＯ８Ｓ’Ｉｉ、界効果トランジ
スタ金形成するために、第１図（ａｌ〜（ｆｌに承丁↓
うに、第１の導電型基板ｌに、熱酸化膜２金成長させ、
フォトリングラフィ技術にニジ窓あけを行ない、基板と
反対の導電型の不純物のイオン注入もしくに、拡散′Ｆ
−エリ、第０不純物領域３を形成しく第１図（ａ））、
さらに全面熱酸化？を除去し、ゲート酸化５を約５ （
１（１〜２０（１（ＩＡ収矢させ、さら（その上（ポリ
シリコンロ全約５００〜６０旧ｌＡ１１ｌｉＸ長させ（
第１図（１）ｌ ） 、フォトリングラフィ技術屹より
１ポリシリコンを例えばＣｌ−１４でドライ・エツチン
グしく第１図（Ｃ））、ポリシリコン（６ａ、６ｂ）？
マスクにして、基板と反対の導′ａ型の不純物のイオン
注入もしくは拡散（より、第１不純物領域７全形成しざ
ら九、同じポリノリコン（６ａ、５ｂ）をマスクにして
、基板と同じ導′亀型の不純物？イオン注入もしくは、
拡散によＶ第２不純物領域８全形成しく第１図（ｄ））
、ポリシリコン（６ｂのみ）全除去し、その上に、例え
ばＣＶＤ酸化膜９を成長させ、さら（フォト・リングラ
フィ技術（より窓あけを行ない鹸化膜エツチングを行な
い、例えばアルミ蒸着を行ない、アルミ電極ｌｏを形成
してきた（第１図（ｅＬ （ｆｌ ） ｏ Ｌかし、第
２図に示し几ように、ボロン拡散プロファイルＨの濃度
プロファイルが、あまりなめらかでない領域でのソース
・リン拡散プロファイル■との交点Ａのボロン濃度によ
りしきい値電圧が、決定している為、しきい値電圧のば
らつきが考えらねる。加えて、第１図（ｆｌ［示しｆＣ
，ようにソース領域８とポリシリコン・ゲート電極領域
が重なっている為、ソース・ケート間に容量が発生し、
スイッチング・スピードが遅くなるという欠点があった
。Conventionally, in order to form planar vertical MO8S'Ii field effect transistor gold,
First, a thermal oxide film of 2 gold is grown on the first conductivity type substrate l,
By making a rainbow window in the photolithography technique, ion implantation or diffusion of impurities of the opposite conductivity type to the substrate is performed.
- Eli, forming the 0th impurity region 3 (FIG. 1(a)),
More complete thermal oxidation? , and gate oxide 5 to approximately 5 (
1 (1 to 20 (1) IA is settled, and further (polysilicon is about 500 to 60 old lA11liX long (
Figure 1 (1)l), using photolithography technology, polysilicon (6a, 6b) is dry etched using, for example, Cl-14 (Figure 1(C)), polysilicon (6a, 6b)?
Using the same polygonal silicone (6a, 5b) as a mask, implant or diffuse ion implantation or diffusion of an impurity of the conductive type A on the opposite side of the substrate (after forming the entire first impurity region 7). Turtle-shaped impurity?Ion implantation or
The entire V second impurity region 8 is formed by diffusion (Fig. 1(d)).
, polysilicon (only 6b) is completely removed, for example a CVD oxide film 9 is grown on it, and then (photo phosphorography technique) apertures are made and saponified film etching is performed, for example aluminum evaporation is performed, aluminum As shown in Figure 2, the concentration profile of the boron diffusion profile H is not very smooth. Since the threshold voltage is determined by the boron concentration at the intersection point A with
, because the source region 8 and the polysilicon gate electrode region overlap, a capacitance is generated between the source and gate.
The drawback was that the switching speed was slow.
本発明の第１の目的は縦型Ｍ（Ｊｆ９・ＦＥＴのしきい
値電圧會さらに安定化することにある。The first object of the present invention is to further stabilize the threshold voltage of the vertical M (Jf9 FET).
第２の目的は、ゲート・ソース間のオーバー・ラップ？
小さくシ、ゲート・ソース間の容量を減少しスイッチン
グ・スピードの速い縦型ＭＯ８・ＦＥＴ１提供すること
にある。The second purpose is overlap between gate and source?
The object of the present invention is to provide a vertical MO8 FET 1 that is small in size, has reduced gate-source capacitance, and has high switching speed.
本発明の特徴は、縦型ＭＯ８−ＦＥＴｒｃおいてポリシ
リコンゲート電極形成後半導体基鈑と反対の導電型を有
する第１不純物領域全形成し、この上に絶縁膜（例えば
ＣＶＤ ８１（Ｊ２もしくは窒化膜）全成長させ、こわ
をスパッタ・エッチにニジエツチングを行ない前記ポリ
シリコンゲート電極側面のみに絶縁膜全残し、前述第１
半導体領域円に半導体基板と同じ導電型の第２の不純物
領域を形式することＶＣある。The feature of the present invention is that after forming the polysilicon gate electrode in the vertical MO8-FETrc, the entire first impurity region having a conductivity type opposite to that of the semiconductor substrate is formed, and an insulating film (for example, CVD 81 (J2 or nitride film) After the entire insulating film is grown, the stiffness is removed by sputter etching, leaving the entire insulating film only on the side surface of the polysilicon gate electrode.
VC is to form a second impurity region of the same conductivity type as the semiconductor substrate in the semiconductor region circle.
本発明（工わば、ゲート電極（例えばポリシリコン）下
のチャンネル形式ｔＣおいて、ゲート電極側面に絶縁膜
が形成されているため、拡散位置が絶縁膜厚だけすわる
ので、第１不純物領域の濃度 ′プロファイ
ルの平たんな領域に＠２不純物領域が形式されるため、
【７さい値電圧の安定化が計わる。In the present invention (in other words, in the channel type tC under the gate electrode (for example, polysilicon)), since an insulating film is formed on the side surface of the gate electrode, the diffusion position is spread by the thickness of the insulating film, so that the first impurity region Since the @2 impurity region is formed in the flat region of the concentration profile,
[7 The stabilization of the minimum voltage is measured.
その上、ゲート電極と、第２不純物領域とのオーバーラ
ツプ長が短かくなるため、ゲート・ソース間の容量が減
少する。従って全体８１ｋが減少し、スイッチング・ス
ピードの同上となる。Furthermore, since the overlap length between the gate electrode and the second impurity region is shortened, the capacitance between the gate and source is reduced. Therefore, the total 81k is reduced and the switching speed is the same.
本発明を、図を用いて詳細に説明する。The present invention will be explained in detail using figures.
従来は、第１図に示す１０セスを用いているが、本発明
では第３図（ａ）〜（ｈ）に示すように第１の導電型基
板１（熱酸化膜を成長させ、フォト・リングラフィ技術
ｖＣより窓あけを行ない、基板と反対の導電型の不純物
イオン注入もしくニ、拡散により１第０不純物領域３ｔ
−形成しく第３図（ａ） ） 、さらに全面酸化膜を除
去し、ゲート酸化膜５約５００〜２０００Ａ成長させ、
ざら（その上に例えばポリシリコンロを約５００〜６０
００ ＡＦｙ、長させ（第３図（ｂ））、フォト・リソ
グラフィ技術ｖｃ↓９、パターンを形成し、ポリシリコ
ンを例えば、ＣＦ４でドライ・エツチングを行ない、ポ
リシリコン、ゲート電極（５ａ、５ｂ）を形式する（第
３図（Ｃ））。ポリシリコン（６ａ、６ｂ）ｔ−マスク
にとし基板と反対の導電型の不純物のイオン注入もしく
ハ、拡散により第１不純物領域７を形成する（第３図（
ｄ） ） ｏさらｒｃそｏ上ｃ絶縁膜例えば、ＣＶＤ
８ｒＯｚ ｅｔｃ １２全約５００Ａ〜数ｐｍＦｆ、長
させ（第３図（ｅ））、その後スパッタエツチングｆ−
より絶縁膜を例えばＣＦ４ｆ用いてエツチング全行なう
。このスパッタ・エツチングは縦方向と横方向のエツチ
ング比率（二縦万同エツチング／横方向エッチングフ数
１０以上あるので第３図（ｆ）（示したようにポリシリ
コン側面の絶縁膜（１２ａ、１２ｂ）が残る。そこで、
ポリシリコン・ゲートを極（６ａ、６ｂ）と絶縁膜（１
２ａ、 １２ｂ ） 全マスクとして基板と同じ導電
型の不純物をイオン注入もしくは、拡散（工り第２不純
物領域８（ソース領域）を形成する（第３図（ｇｌ、
（ｈｌ ） ｏこのようにして形式すると、第３図（ｈ
）（示すようＶＣ第１不純物領域７と第２不純物領域８
との拡散位置が各々ＢとＣとなり絶縁膜厚ｔの長さだけ
ずれる。従って、第１不純物領域７の拡散プロファイル
のなだらかな部分と、第２不純物領域８が交わる為、し
きい値電圧が安定化する。さら（加えて、ゲート（６ａ
）とソース領域（８）のオーバーラツプが短かくなる為
容量が減少する。さらにポリＳ１及び絶縁膜（６ａ、
１２ｂ） Ｔｈ除去し、その上に、例えばＣＶＤ酸化膜
９を成長させ、さらに、フォトリソグラフィ技術にエフ
窓あけ全行ない、酸化膜エツチングを行ない例えばアル
ぐ蒸着を行ない、アルミ電極１０全形成する。Conventionally, 10 cells shown in FIG. 1 are used, but in the present invention, as shown in FIGS. A window is opened using phosphorography technology vC, and impurity ions of a conductivity type opposite to that of the substrate are implanted or diffused to form the 10th impurity region 3t.
- After the formation (Fig. 3(a)), the entire oxide film is removed, and a gate oxide film of about 500 to 2000 A is grown.
Coarse (approximately 500 to 60
00 AFy, lengthen (Fig. 3(b)), form a pattern using photolithography technique vc↓9, dry-etch the polysilicon with, for example, CF4, and form the polysilicon and gate electrodes (5a, 5b). (Figure 3 (C)). A first impurity region 7 is formed by ion implantation or diffusion of an impurity of a conductivity type opposite to that of the substrate using a polysilicon (6a, 6b) T-mask (see FIG. 3).
d)) Insulating film on rc, for example, CVD
8rOz etc. 12 total length of about 500A to several pmFf (Fig. 3(e)), then sputter etching f-
The entire etching process is then carried out using, for example, CF4f as the insulating film. This sputter etching has a vertical and horizontal etching ratio (two vertical etching/horizontal etching ratios of 10 or more), as shown in Figure 3(f). ) remains.Therefore,
The polysilicon gate is connected to the poles (6a, 6b) and the insulating film (1
2a, 12b) A second impurity region 8 (source region) is formed by ion implantation or diffusion (processing) with an impurity of the same conductivity type as the substrate as a whole mask (see Fig. 3 (gl, 12b).
(hl) o When formatted in this way, Figure 3 (h
) (As shown, VC first impurity region 7 and second impurity region 8
The diffusion positions of B and C are respectively shifted by the length of the insulating film thickness t. Therefore, since the gentle portion of the diffusion profile of the first impurity region 7 intersects with the second impurity region 8, the threshold voltage is stabilized. Sara (in addition, gate (6a
) and the source region (8) becomes shorter, the capacitance decreases. Further, poly S1 and insulating film (6a,
12b) After removing Th, for example, a CVD oxide film 9 is grown thereon, and further, an F window is completely opened using photolithography, the oxide film is etched, and, for example, Al is evaporated to form an aluminum electrode 10.
本発明によれば、縦形ＭＯ８−ＦＥＴにおいて、第２ゲ
ート形成（第１不純物領域）とソース領域（第２不純物
領域）を形成する時に絶縁膜をスパッタエッチによりゲ
ート電極側面に残り拡散位置をずらすことＶＣ工、０第
２不純物領域の濃度ズロファイルのなだらかな部分（第
３不純物領域が形成される為しきい値電圧の安定化が計
れる。加えて、ゲート電極とソース領域のオーバー・ラ
ップが短かくなる為容量減少し、スイッチング・スピー
ドの同上が針引る。According to the present invention, in a vertical MO8-FET, when forming the second gate (first impurity region) and source region (second impurity region), the insulating film is left on the side surface of the gate electrode by sputter etching and the diffusion position is shifted. Also known as VC engineering, the gradual part of the concentration slope profile of the second impurity region (because the third impurity region is formed, the threshold voltage can be stabilized.In addition, the overlap between the gate electrode and the source region is short). As a result, the capacity decreases and the switching speed increases.
第１図（ａ）〜（ｆ）は各々従来の製造工程ケ示す断面
図、Ｍ２図に第２，３不純物領域の拡散クロファイル、
第３図（ａ）〜（ｈ）［各々本発明実施例の製造工程全
示す断圓図、でめる。
なお図（おいて、ｌ・・・−導電型基板、２・・・酸化
膜、３・・・基板と反対の導電型の第０不純物領域、５
・・・ゲート酸化膜、６・・・ゲート・ポリシリコン（
ゲート電極）、（６ａ、６ｂ） ７・・・基板と反対
の導電型の第１不純物領域（第２ゲート領域ン、８・・
・基板と同じ導電型の第２不純物領域（ソース領域２．
９・・・ＣＶＤ ８ｉ０２（絶縁膜］、１０・・・アル
ミニウム電極（ソース電極）、１１・・・ドレイン電極
、１２−・・絶縁膜、（１２ａ、１２ｂ） Ｌ−・・チ
ャンネル長、ｍ・・・第２不純物領域拡散長、Ｘ・・・
横方向拡散距離、Ｂ・・・第１不純物領域拡散窓、Ｃ・
・・第２不純物領域拡散窓、である。
予冷）、
代理人 弁理士 内 原 音（１，−、、、、“
）（ｂ）
笛ｆ＋
２１ （ナノ
（θ）（ｄ）
（ｆ！Ｌ。
第３Figures 1 (a) to (f) are cross-sectional views showing the conventional manufacturing process, and Figure M2 shows the diffusion profiles of the second and third impurity regions.
FIGS. 3(a) to 3(h) are cross-sectional views showing the entire manufacturing process of the embodiments of the present invention. In addition, in the figure (l... - conductivity type substrate, 2... oxide film, 3... 0th impurity region of conductivity type opposite to the substrate, 5
...Gate oxide film, 6...Gate polysilicon (
gate electrode), (6a, 6b) 7... first impurity region (second gate region) of the conductivity type opposite to that of the substrate, 8...
- A second impurity region (source region 2.
9...CVD 8i02 (insulating film), 10...aluminum electrode (source electrode), 11...drain electrode, 12-...insulating film, (12a, 12b) L-...channel length, m. ...Second impurity region diffusion length, X...
Lateral diffusion distance, B...first impurity region diffusion window, C...
...Second impurity region diffusion window. Pre-cooling), Agent Patent Attorney Uchihara Oto (1,-,,,,“
)(b) Whistle f+ 21 (nano(θ)(d) (f!L. 3rd
Claims (1)
、前述ゲート酸化膜上にポリシリコンを成長させ、該ポ
リシリコンをエツチングして制御電極？形成し、該エツ
チングしてポリシリコンの除去された部分に逆導電型不
純物を導入して第１の半導体領域を形成し、さらにこの
上Ｙこ、第１の絶縁物を成長させ、さらにスパッタ・エ
ツチングを行ないＨ記ポリ・シリコンの側面のみに前記
第１の絶縁物を残しさら（前記ｉｌｌの半導体領域内に
一導電型の第２の不純物領域？形成することを特徴とす
る縦型電界効果トランジスタの製造方法。[Claims] One conductivity type? [Grow a gate oxide film, grow polysilicon on the gate oxide film, and etch the polysilicon to form a control electrode.] A first semiconductor region is formed by introducing impurities of opposite conductivity into the portion where the polysilicon is removed by etching, and then a first insulator is grown on top of the first semiconductor region. A vertical field effect characterized by etching, leaving the first insulator only on the side surfaces of the polysilicon (H), and forming a second impurity region of one conductivity type in the semiconductor region of the ill. Method of manufacturing transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58088002A JPS59213168A (en) | 1983-05-19 | 1983-05-19 | Manufacture of vertical type field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58088002A JPS59213168A (en) | 1983-05-19 | 1983-05-19 | Manufacture of vertical type field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59213168A true JPS59213168A (en) | 1984-12-03 |
Family
ID=13930570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58088002A Pending JPS59213168A (en) | 1983-05-19 | 1983-05-19 | Manufacture of vertical type field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59213168A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01225164A (en) * | 1988-03-03 | 1989-09-08 | Fuji Electric Co Ltd | Manufacture of insulated gate mosfet |
| JPH01270359A (en) * | 1988-04-22 | 1989-10-27 | Nec Corp | Manufacture of vertical type field-effect transistor |
| JP2004207476A (en) * | 2002-12-25 | 2004-07-22 | Mitsubishi Electric Corp | Power semiconductor device, and method for manufacturing the same |
-
1983
- 1983-05-19 JP JP58088002A patent/JPS59213168A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01225164A (en) * | 1988-03-03 | 1989-09-08 | Fuji Electric Co Ltd | Manufacture of insulated gate mosfet |
| JPH01270359A (en) * | 1988-04-22 | 1989-10-27 | Nec Corp | Manufacture of vertical type field-effect transistor |
| JP2004207476A (en) * | 2002-12-25 | 2004-07-22 | Mitsubishi Electric Corp | Power semiconductor device, and method for manufacturing the same |
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