JPS5921183B2 - charge coupled device - Google Patents
charge coupled deviceInfo
- Publication number
- JPS5921183B2 JPS5921183B2 JP50010383A JP1038375A JPS5921183B2 JP S5921183 B2 JPS5921183 B2 JP S5921183B2 JP 50010383 A JP50010383 A JP 50010383A JP 1038375 A JP1038375 A JP 1038375A JP S5921183 B2 JPS5921183 B2 JP S5921183B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- substrate
- charge
- electrode
- potential well
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 69
- 239000000758 substrate Substances 0.000 claims description 19
- 238000011144 upstream manufacturing Methods 0.000 claims description 9
- 239000000969 carrier Substances 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 3
- 239000013078 crystal Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910007709 ZnTe Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 210000001525 retina Anatomy 0.000 description 1
- SBIBMFFZSBJNJF-UHFFFAOYSA-N selenium;zinc Chemical compound [Se]=[Zn] SBIBMFFZSBJNJF-UHFFFAOYSA-N 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/282—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1062—Channel region of field-effect devices of charge coupled devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76866—Surface Channel CCD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76866—Surface Channel CCD
- H01L29/76875—Two-Phase CCD
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
【発明の詳細な説明】
本発明は、基板が互に異なる禁止帯
(forbiddenband)の巾をもつ2個の半導
体によつて形成されていて電子技術分野、特にシフトレ
ジスタ、遅延ライン、記憶システム、レチナ(reti
na)等の分野に応用可能の電荷結合装置(charg
e−coupleddevice)に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention is particularly useful in the field of electronic technology, particularly shift registers, delay lines, storage systems, etc., in which the substrate is formed by two semiconductors having mutually different forbidden band widths. Retina (reti)
charge-coupled devices (charg) that can be applied to fields such as
e-coupled devices).
電荷結合装置(CCDと略す)は、半導体の表面につく
られた電位井戸(potentialwell)内に電
荷が蓄積されていて該電位井戸を変位することによつて
これらの電荷が移動される半導体システムである。A charge-coupled device (abbreviated as CCD) is a semiconductor system in which charges are accumulated in a potential well formed on the surface of a semiconductor, and these charges are transferred by displacing the potential well. be.
極めて一般的に述べると、これらの装置は、ドープした
半導体基板と、絶縁材料層と、適当な電位とされる金属
電極の列とを含む。それ故、この構造は金属−絶縁体−
半導体型のもので、絶縁体は特に酸化物によつて構成で
きる。この型式の装置においてこの方法で変位される電
荷は、半導体基板の少数キャリヤ、例えば半導体がn型
の場合、ホールである。これらの電荷結合装置の一般的
性質に関する基礎的情報としては、「ベル・システム・
テクニカル・ジャーナル」(BellSystemTe
chnicalJournal)1970年第49巻に
掲載されているW−S・ポール(Boyle)およびG
、E、スミス(Smlth)両氏の「電荷結合半導体装
置」と題する論文(587ページ)およびG、F、アメ
リオ(AmeliO′).M.F.トップセット(TO
Olpsett)およびJ.E.スミス(Smith)
三氏の「電荷結合装置の思想の実験的証明」と題する論
文を参照できる。Very generally speaking, these devices include a doped semiconductor substrate, a layer of insulating material, and an array of metal electrodes at an appropriate potential. Therefore, this structure is metal-insulator-
It is of the semiconductor type, and the insulator can be composed of an oxide, in particular. The charges displaced in this way in this type of device are minority carriers in the semiconductor substrate, for example holes if the semiconductor is n-type. For basic information on the general properties of these charge-coupled devices, see the Bell System
Technical Journal” (BellSystemTe)
W.S. Paul (Boyle) and G. Chnical Journal) published in Volume 49, 1970.
, E. Smlth (page 587) and G. F. AmeliO'. M. F. Top set (TO
Olpsett) and J. E. Smith
You can refer to Mr. San's paper titled ``Experimental proof of the idea of a charge-coupled device.''
これらの装置においては、電荷の移動を一方向性とする
ことが必要で、従つて、少数キヤリヤに対して上流端に
おけるよりも下流端において深さが大きくなつている非
対称形の電位井戸をつくることが必要である。In these devices, it is necessary for the charge transfer to be unidirectional, thus creating an asymmetrical potential well for the minority carriers that is deeper at the downstream end than at the upstream end. It is necessary.
この型式の井戸をつくるための多くの手段が知られてい
る。例えば、3個のクロツクを使用し、相互に交又する
3個の制御ラインによつて各クロツクを3個の中の1つ
の電極に接続することができ、このクロツクおよび関連
する制御ラインの数を2個に減少するためには、電極の
上流縁の下で電極残部の下よりも強くドープされている
表面区域を半導体内で1つの電極の下に形成することが
可能である。本発明は、この型式の装置内に電荷移動の
一方向性を得るための新規な手段を提案するもQである
。Many means are known for creating wells of this type. For example, three clocks can be used, each clock connected to one of the three electrodes by three intersecting control lines, and the number of clocks and associated control lines In order to reduce this to two, it is possible to create a surface area in the semiconductor under one electrode that is more heavily doped under the upstream edge of the electrode than under the rest of the electrode. The present invention proposes new means for obtaining unidirectionality of charge transfer within this type of device.
一般的に、この手段は、非対称的な井戸をつくろうとす
る領域内に、異なる禁止帯の巾をもつ2個の異なる半導
体を置くことにある。以後の説明から明らかとなるよう
に、この解決法は多くの利点を与え、特に、これは非常
に簡単な製作法を与え且つこれが適用された電荷結合装
置の性質の改良を生ずる。特に、本発明は、第1のドー
プされた半導体によつて構成された基板と、軸線に沿つ
て順次に配置され薄い絶縁層により該基板から隔離され
た金属電極の列と、少数電荷キヤリヤに対して上流方向
よりも下流方向に深さの大きくなつている非対称形電位
井戸を基板の表面領域内につくりかくして該軸線に沿つ
て該キヤリヤの移動の一方向性を確保する手段と、少数
キヤリヤを少くとも第1の電極の下に注入する手段と、
少くとも該電極の下の電荷の存在を検出する手段と、電
極を適当な値の循環的に変化する電位とする手段とを備
えた電荷結合装置に関するものである。Generally, this consists in placing two different semiconductors with different bandgap widths in the region where the asymmetric well is to be created. As will become clear from the following description, this solution offers many advantages, in particular it provides a very simple manufacturing method and results in an improvement in the properties of the charge-coupled device to which it is applied. In particular, the invention provides a substrate constituted by a first doped semiconductor, an array of metal electrodes arranged sequentially along an axis and separated from the substrate by a thin insulating layer, and a minority charge carrier. means for ensuring unidirectionality of movement of the carrier along the axis by creating an asymmetrical potential well in the surface area of the substrate, the depth of which is greater in the downstream direction than in the upstream direction; means for injecting the at least one electrode below the first electrode;
The present invention relates to a charge-coupled device comprising at least means for detecting the presence of a charge under the electrode and means for placing the electrode at a cyclically varying potential of an appropriate value.
上記の基板の表面区域内に非対称的な電位井戸を生じ該
キヤリヤの移動の一方向性を確保する手段は、該区域の
一端部で該基板内に位置し第1の半導体とは異なる禁止
帯巾をもつ第2の半導体により形成される領域によつて
構成され、上記の小さい方の禁止帯巾をもつ1方の半導
体が上記の区域の下流に位置している。本発明の特徴お
よび利点は、次に図面を参照して説明する本発明の構成
の例から明らかとなるであろう。Means for creating an asymmetric potential well in the surface area of the substrate and ensuring unidirectionality of movement of the carrier includes a forbidden band located in the substrate at one end of the area and different from the first semiconductor. a region formed by a second semiconductor having a width, one semiconductor having the smaller bandgap being located downstream of the region; The features and advantages of the invention will become clear from the examples of configurations of the invention which will now be described with reference to the drawings.
この構成は、例示として記載するもので本発明を全く制
限するものではない。下記の説明において、少数キヤリ
ヤ(これは、ここに説明する装置における移動する電荷
である)がホールであるn型半導体Q例についてのみ説
明する。This configuration is provided as an example and is not intended to limit the invention in any way. In the following discussion, only the n-type semiconductor Q example will be discussed where the minority carriers (which are the moving charges in the device described here) are holes.
第1図の概略図は、異なる巾の2つの禁止帯をもつ2個
の半導体の異なる帯のエネルギー分布を示す。The schematic diagram of FIG. 1 shows the energy distribution of different bands of two semiconductors with two forbidden bands of different widths.
左側の部分は、EClで示すエネルギーをもつ伝導帯お
よびEVlで示すエネルギーをもつ価電子帯(Vale
nceband)を含む半導体SClに相当する。同様
に、右側の部分は、EC2によつて示すエネルギーをも
つ価電子帯を含む半導体SC2を示す。これらの2つの
半導体の接合部において、平衡が得られる時にEFで示
すエネルギーのフエルミ準位は一致する。固有エネルギ
ーは、定義により伝導帯のエネルギーと価電子帯のエネ
ルギーの間の平均エネルギーのことである。半導体理論
における従来の考察から、価電子帯に関するフエノルミ
準位の位置は下記の関係によつて定義されることとなる
。N.,
ここで、E8は禁止帯の巾に等しく、すなわち、Ec−
Evで、Kはボルツマン定数、Tは絶対温度Ncは温度
および電荷キヤリヤの質量のみによて定まる定数、ND
負はキヤリヤの密度である。The left part shows the conduction band with energy shown as ECl and the valence band with energy shown as EVl.
nceband). Similarly, the right-hand part shows a semiconductor SC2 containing a valence band with an energy denoted by EC2. At the junction of these two semiconductors, when equilibrium is achieved, the Fermi levels of energies indicated by EF coincide. Eigenenergy, by definition, is the average energy between the conduction band energy and the valence band energy. From conventional considerations in semiconductor theory, the position of the phenolmi level with respect to the valence band is defined by the following relationship. N. , where E8 is equal to the width of the forbidden band, that is, Ec-
Ev, K is the Boltzmann constant, T is the absolute temperature, Nc is a constant determined only by the temperature and the mass of the charge carrier, ND
Negative is the density of the carrier.
半導体SC2の価電子帯のエネルギーを半導体SClの
価電子帯のエネルギーより大きくすることが望まれるな
らば、下記の条件を満足しなければならない。ここで、
NDlおよびND2は半導体SClおよびSC2のドー
ピングを特性ずけるものである。If it is desired to make the valence band energy of the semiconductor SC2 larger than the valence band energy of the semiconductor SCl, the following conditions must be satisfied. here,
NDl and ND2 characterize the doping of the semiconductors SCl and SC2.
不等式(1)は下記の不等式と等価であるOドーピング
NDlおよびND2および定数NClおよびNC2が密
接に関連すれば、不等式(2)は禁止帯EglおよびE
g2のエネルギーが僅かに異なる(これが実際の場合で
ある)と直ちに満足される。Inequality (1) is equivalent to the following inequality: If the O dopings NDl and ND2 and the constants NCl and NC2 are closely related, then the inequality (2) becomes the forbidden band Egl and E
It is immediately satisfied that the energies of g2 are slightly different (which is the case).
例としてシリコンとゲルマニウムの場合を考えると、E
gはそれぞれ1.1evおよび0.7evで、従つて、
禁止帯の値の間に0.4evの差がある。この型式の1
対の半導体の場合、式(2)の指数の大きさは非常に小
さく、ドーピングおよび定数Ncが相互に余り相違して
なければ、不等式は満足される。価電子帯の状態は、第
1図のダイアグラムに示す場合のようになつている。Considering the case of silicon and germanium as an example, E
g are 1.1ev and 0.7ev, respectively, so
There is a difference of 0.4ev between the forbidden band values. 1 of this model
In the case of paired semiconductors, the magnitude of the exponent in equation (2) is very small and the inequality is satisfied if the doping and the constant Nc are not too different from each other. The state of the valence band is as shown in the diagram of FIG.
この図から、半導体SClのホール、従つて、電荷結合
装置内で移動される電荷は半導体SClの価電子帯から
半導体SC2の価電子帯に向けて動くように拘束される
こととなる。かくて、本発明の主たる目的である一方向
形態で少数キヤリヤに働く電界がつくられる。第1図は
一般的な場合に関するものであるが、ドーピングおよび
定数NCが密に関連する場合、換言するとNDl+ND
・2でNCl≠NO2の場合、伝導帯のエネルギーEC
lおよびEOiは非常に近い値となるであろう。From this figure, it follows that the holes in the semiconductor SCl and therefore the charges transferred in the charge-coupled device are constrained to move from the valence band of the semiconductor SCl towards the valence band of the semiconductor SC2. Thus, an electric field is created which acts in the minority carrier in a unidirectional manner, which is the main object of the invention. Although Figure 1 concerns the general case, when doping and constant NC are closely related, in other words NDl+ND
・If NCl≠NO2 in 2, the conduction band energy EC
l and EOi will have very close values.
同様に、フエルミエネルギ一と固有エネルギーの差を計
算することによつて、半導体SClおよびSC2の2つ
の固有エネルギーが下記の特定の場合に一致することを
認めることができる。これは次のようにかくことができ
る。Similarly, by calculating the difference between the Fermi energy and the characteristic energy, it can be seen that the two characteristic energies of the semiconductors SCl and SC2 coincide in the specific case below. This can be written as follows.
nlは対応する固有の半導体についての伝導帯における
電荷の密度(あるいは、これに等しい価電子帯内のホー
ルの数)である。nl is the density of charges in the conduction band (or equivalently the number of holes in the valence band) for the corresponding native semiconductor.
それ故、2つの禁止帯の間に充分なエネルギーの差があ
れば、2個の半導体のドーピングを制御する条件は厳密
なものではないことが前記の説明から明らかである。Therefore, it is clear from the above explanation that the conditions controlling the doping of the two semiconductors are not critical, as long as there is a sufficient energy difference between the two forbidden bands.
実際上、2つのドーピングが殆んど同じである状態を採
用し、これにより、製作を簡単化するのが有利である。
第2a図に、第1の半導体SClに、この第1の半導体
とは異なる禁止帯の巾をもつ第2の半導体SC2によつ
て構成される領域を付加することによつて非対称形電位
井戸がつくられている電荷結合装置の区域の断面が示さ
れている。In practice, it is advantageous to adopt a situation in which the two dopings are almost the same, thereby simplifying the fabrication.
In FIG. 2a, an asymmetric potential well is created by adding to the first semiconductor SCl a region constituted by a second semiconductor SC2 having a forbidden band width different from that of the first semiconductor. A cross-section of the area of the charge-coupled device being constructed is shown.
第2図のダイアグラムにおいて、半導体S。2が少数キ
ヤリヤの移動の方向Dに関して下流に配置されていると
仮定する。In the diagram of FIG. 2, semiconductor S. 2 is located downstream with respect to the direction D of movement of the minority carrier.
第1図のダイアグラムから、半導体SC2が禁止帯の巾
が最小のものであることがわかる。半導体SClがシリ
コンならば、この半導体SC2は例えばゲルマニウムで
ある。この装置は、2個の半導体SClおよびSC2の
外に、絶縁層10を備え、これは任意の所望の形を有し
、図示してない他の装置を支持できそしてこれは電荷装
置の特徴である。第2bは第2a図に示す区域に沿う表
面電位V8の形を示す。From the diagram in FIG. 1, it can be seen that the semiconductor SC2 has the smallest forbidden band width. If the semiconductor SCl is silicon, the semiconductor SC2 is, for example, germanium. Besides the two semiconductors SCl and SC2, the device comprises an insulating layer 10, which has any desired shape and can support other devices not shown, and which is characteristic of a charge device. be. 2b shows the shape of the surface potential V8 along the area shown in FIG. 2a.
この電位は半導体10の間の界面の電位である。少数キ
ヤリヤは半導体SC2に引きつけられるので、電位井戸
は、この区域の残部におけるよりも半導体SC2のレベ
ルで大きい深さをもつている。従つて、これによつて第
2a図に示す形の段のついて形態を生ずる。半導体SC
lに、より小さい巾の禁止帯をもつ第2の半導体SC2
を加えることによつて、これは、上流方向よりも下流方
向に深さの大きくなる非対称的な表面電位井戸をつくる
ための有効な手段を構成し、電荷結合装置間に電荷移動
の一方向性を得るように伝導する。第3図および第4図
は前記の手段を電荷結合装置に応用したものを示す。This potential is the potential of the interface between the semiconductors 10. Since minority carriers are attracted to semiconductor SC2, the potential well has a greater depth at the level of semiconductor SC2 than in the rest of this area. This therefore results in a stepped configuration of the form shown in Figure 2a. semiconductor SC
a second semiconductor SC2 having a smaller forbidden band in l;
By adding conduct so as to obtain. 3 and 4 show the application of the above means to a charge-coupled device.
第3図には単一の制御ラインをもつ電荷結合装置が示さ
れている。FIG. 3 shows a charge coupled device with a single control line.
第3a図はこの型式の装置の断面図で、第1の半導体S
Clを示し、その上に絶縁層12および電極14が置か
れ、電極14は総て2つの制限値V1とV2の間で循環
的に変化する電圧VGを送るように構成された電圧供給
装置18からのりード線16に接続されている。FIG. 3a is a cross-sectional view of a device of this type, in which the first semiconductor S
Cl, on which are placed an insulating layer 12 and an electrode 14, the electrodes 14 all being configured to deliver a voltage VG varying cyclically between two limit values V1 and V2. It is connected to the lead wire 16 from the terminal.
さらに、第3a図の装置は、一方では、電極の下に第2
の半導体SC2によつて構成された領域20を有し、且
つ他方では電極間の間隙内に同じ半導体SC2により構
成された同一の領域22を有している。Furthermore, the device of FIG. 3a, on the one hand, has a second
on the other hand, and on the other hand, it has an identical region 22 formed of the same semiconductor SC2 in the gap between the electrodes.
半導体SClと絶縁体12の間の界面の表面電位は第3
b図に示すように装置に沿つて変化する。The surface potential of the interface between the semiconductor SCl and the insulator 12 is the third
b varies along the device as shown in figure b.
電圧VGが所定値の場合、各電極の下に位置した2半導
体区域の性質に従つて上流方向よりも下流方向に深さの
大きくなつている非対称形電位井戸が各電極の下に観察
される。これらの井戸の深さは電極14に印加される電
圧VGによつて定まる。電圧VGの2つの制限値V1お
よびV2に関するこれらの電位の2つの値は第3b図に
示されている。伺じ理由で、上流方向よりも下流方向に
深さの大きくなる非対称形の電位井戸が電極間間隙内に
見られるが、電極間間隙内の表面電位は電極に印加され
る電位には殆んど無関係であつて表面抵抗が適当に選択
される時に充分な時間的間隔の終りでV,と2の平均値
に定められるので、上記の井戸は永久的である。こ\で
、注目すべき事項は、リード線16と同様のラインによ
つて前記の平均値に等しい定電位源に接続され第1の電
極の間に介在した電極の第2の組を使用することも可能
であることである。そうすると、装置は直ちに動作でき
る状態にあるが、さらに複雑である。本発明による電荷
結合装置の動作は次の通りである。印加される電圧VG
がV1 (原則的に、この電圧はn型基板の場合に負で
ある)に等しい時、電極の下につくられる電位井戸の深
さは最大で正電荷が下流区域内でその中に捕捉される。
電圧Gが値2となる時、電極14の下の電位井戸の深さ
は減少され、その中に捕捉し得る電荷は、直接に隣接し
て下流側に位置した電極間間隙の永久的な非対称電位井
戸の中に移動される。これらの電荷は、電圧Gが値1に
戻る時に、後続の電極の下につくられた電位井戸内に移
される。電圧Gは任意の波形をもつことができて、例え
ば矩形波でよい。満足すべき唯一の条件は、V1および
V2の値が、電極の下流側の電位井戸の最小深さが電極
間間隙の上流側の電位井戸の深さよりも小さくなるよう
な値とすることで、且つ電極の上流の電位井戸の最大深
さが電極間間隙の下流の電位井戸の深さよりも大きくな
ければならないことである。このような条件において、
電荷の移動は、電圧サイクルの間、先ず電極の下に位置
した区域から電極間間隙に向けて、次にこの電極間間隙
から後続の電極の下に位置した区域に向けて正しく生じ
得る。電荷の移動の一方向性を生ずるための本発明によ
る最初の手段は、単に、単一制御ラインをもつ電荷結合
装置に適用されるのみならず、例示として第4図に示す
型式の2個の制御ラインをもつ電荷結合装置にも適用さ
れる。For a given voltage VG, an asymmetrical potential well is observed under each electrode, which is deeper in the downstream direction than in the upstream direction, depending on the nature of the two semiconductor regions located under each electrode. . The depth of these wells is determined by the voltage VG applied to electrode 14. The two values of these potentials for the two limit values V1 and V2 of the voltage VG are shown in FIG. 3b. For the same reason, an asymmetrical potential well with a deeper depth in the downstream direction than in the upstream direction is observed within the interelectrode gap, but the surface potential within the interelectrode gap is almost independent of the potential applied to the electrodes. The well is permanent since it is determined to be the average value of V, and 2 at the end of a sufficient time interval, regardless of the surface resistance being properly chosen. It should be noted here that the use of a second set of electrodes interposed between the first electrodes is connected by a line similar to lead 16 to a constant potential source equal to said average value. It is also possible. The device is then ready for operation, but with added complexity. The operation of the charge-coupled device according to the invention is as follows. Applied voltage VG
is equal to V1 (in principle, this voltage is negative for an n-type substrate), the depth of the potential well created under the electrode is at most such that positive charges are trapped in it in the downstream area. Ru.
When the voltage G takes a value of 2, the depth of the potential well below the electrode 14 is reduced and the charge that can be trapped therein is reduced due to the permanent asymmetry of the immediately adjacent downstream electrode gap. potential is moved into the well. These charges are transferred into the potential well created under the subsequent electrode when the voltage G returns to the value 1. The voltage G can have any waveform, for example a rectangular wave. The only condition to be satisfied is that the values of V1 and V2 be such that the minimum depth of the potential well downstream of the electrode is less than the depth of the potential well upstream of the interelectrode gap; and the maximum depth of the potential well upstream of the electrodes must be greater than the depth of the potential well downstream of the interelectrode gap. Under such conditions,
The transfer of charge can take place during the voltage cycle, first from the area located under the electrode towards the interelectrode gap, and then from this interelectrode gap towards the area located under the subsequent electrode. The first means according to the invention for producing unidirectional charge transfer applies not only to charge-coupled devices with a single control line, but also to two charge-coupled devices of the type shown in FIG. It also applies to charge-coupled devices with control lines.
この装置は、第1の半導体SClによつて構成された基
板と、絶縁層30とを有し、この絶縁層の上に、電極3
2,34が配置され、これはリード線32′,34′に
接続され、これらのリード線は2つのクロツク321,
341に接続される。電荷移動の一方向性を生ずるため
の手段は、半導体SClより小さい禁止帯巾をもつ第2
の半導体SC2によつて構成され各電極の下流端の下に
配置された領域40を付加することによつて構成される
。この状態において、上流方向よりも下流方向において
大きい深さをもつ非対称形電位井戸が各電極の下につく
られ、かくして形成された装置は2つの制御ラインをも
つ電荷結合装置と同じようにして動作する。例として1
972年1月14日出願の特願昭47−6408、或い
は「1EEEジヤーナル.オブ.ソリツド。ステート.
サーキツト」(1EEEJ0urna10fS011d
StatesCircuits)1971年10月、第
6巻、第5号に掲載された「電荷結合デイジタルサーキ
ツト」と題するW.F.コソノツキ(KOsOnOck
y)およびG.E.カームス(Carmes)の論文を
参照できる。1個または2個の制御ラインを含む上記の
2つの電荷結合装置において、半導体基板全体に補正を
行い、かくして、VOおよびV2の正しい値が接地に関
して対称的となるように電圧Vsを調整することが常に
可能である。This device has a substrate made of a first semiconductor SCl and an insulating layer 30, and an electrode 3 is placed on the insulating layer.
2, 34 are arranged, which are connected to lead wires 32', 34', and these lead wires are connected to two clocks 321, 34'.
341. The means for producing unidirectionality of charge transfer is the second one having a smaller bandgap than the semiconductor SCl.
by adding a region 40 made up of semiconductor SC2 and placed under the downstream end of each electrode. In this situation, an asymmetrical potential well with a greater depth in the downstream direction than in the upstream direction is created under each electrode, and the device thus formed operates in the same way as a charge-coupled device with two control lines. do. As an example 1
Patent Application No. 47-6408 filed on January 14, 1972, or “1EEE Journal of Solid State.
circuit” (1EEEJ0urna10fS011d
``Charge Coupled Digital Circuits,'' published in October 1971, Vol. 6, No. 5. F. Kosonotsuki (KOsOnOck)
y) and G. E. Reference may be made to the paper by Carmes. In the above two charge-coupled devices containing one or two control lines, a correction is made across the semiconductor substrate, thus adjusting the voltage Vs so that the correct values of VO and V2 are symmetrical with respect to ground. is always possible.
説明のために前に仮定したように半導体がn型の場合、
この目的で、例えば硼素のイオンインプランテーシヨン
によつて、半導体土に均一のp型の付着を適用すること
が可能であろう。接地に関して対称的な電圧をもつとい
う利点に加えて、この構造の変型は少数キヤリヤの移動
するチヤンネルを「埋設」(Bury)することを可能
とし、これにより、半導体の表面における再結合を排除
し装置の性能を改良する。本発明による手段の第1の利
点は、本発明がプレーナ一型電荷結合装置を提供するこ
ととなり、換言すると、電位の形態が段付きでなく先行
技術の同等の装置に比して極めて簡単化した装置を提供
することとなることにある。第2の利点は、単一の制御
ラインをもつ電荷結合装置が極めて容易に製造できると
いう事実にある。いずれの場合にも、本発明によつて提
案される解決はドーピングに関して厳密な条件を伴うこ
とがない。特に、ドーピングは軽い必要はなく、従つて
、これはキヤリヤの再結合の影響を制限する。本発明の
適用にとつて必要な半導体基板を形成するために、2つ
の異なる半導体の小さい巾の結晶を並置したり、或いは
、第1の型の半導体の大サイズの結晶の中に他の型の半
導体の小さい巾の結晶の列を導入することは容易である
ことは明らかである。If the semiconductor is n-type as assumed earlier for explanation, then
For this purpose, it would be possible to apply a uniform p-type deposit to the semiconductor soil, for example by ion implantation of boron. In addition to the advantage of having symmetrical voltages with respect to ground, this structural variant makes it possible to "bury" the moving channels of minority carriers, thereby eliminating recombination at the surface of the semiconductor. Improve equipment performance. A first advantage of the measure according to the invention is that it provides a planar charge-coupled device, in other words, the form of the potential is not stepped and is extremely simplified compared to comparable devices of the prior art. The goal is to provide a device that is A second advantage lies in the fact that charge-coupled devices with a single control line are extremely easy to manufacture. In any case, the solution proposed by the invention does not involve strict conditions regarding doping. In particular, the doping need not be light, so this limits the influence of carrier recombination. In order to form the semiconductor substrate necessary for the application of the invention, small-width crystals of two different semiconductors may be juxtaposed, or a large-sized crystal of a first type of semiconductor may be placed inside a large-sized crystal of a semiconductor of another type. It is clear that it is easy to introduce arrays of small width crystals of semiconductors.
このような構造の形態は実際的であるよりも理論的であ
ると思われ、所望の結果を得る最も便宜な方法は、第1
の型の半導体の大サイズの結晶から始め、他の型の半導
体の原子を入れることによつて、小さい巾の区域の列を
なして上記の第1の型の半導体の禁止帯巾内に局部的な
変化を生ぜしめることである。このようにして形成され
た区域の禁止帯の巾は第2の型の半導体に相当する最大
巾まで順次に変化できる。上記の方法による半導体の製
造は拡散技術によつて実施できるが、イオンインプラン
テーシヨンによつてさらに容易に達成できる。Such a form of construction appears to be more theoretical than practical, and the most convenient way to obtain the desired result is to
Starting from a large-sized crystal of a semiconductor of the type mentioned above, by introducing atoms of the other type of semiconductor, a row of areas of small width can be formed locally within the bandgap of the first type of semiconductor mentioned above. The goal is to bring about significant change. The width of the forbidden zone of the area thus formed can be varied sequentially up to a maximum width corresponding to the second type of semiconductor. The production of semiconductors according to the method described above can be carried out by diffusion techniques, but is more easily achieved by ion implantation.
前記に挙げたシリコンおよびゲルマニウムの例は本発明
を制限しようとするものではなく、特に、シリコン基板
の中に、例えばGaAS,.Gap.GaSぺ1nAs
,.1np,.1nSbのようなl−型或いは0dSe
10dTr,.ZnSe,.ZnTeのような−型の化
合物半導体によつて構成された区域をつくることが可能
である。The examples of silicon and germanium mentioned above are not intended to limit the invention, and in particular, silicon substrates such as GaAS, . Gap. GaSpe1nAs
、. 1np,. l-type such as 1nSb or 0dSe
10dTr,. ZnSe,. It is possible to create areas constituted by -type compound semiconductors such as ZnTe.
上記の場合、複合半導体の2つの要素のイオンの順次の
2つのインプランテーシヨンを実施することが必要であ
るに過ぎない。In the above case, it is only necessary to carry out two successive implantations of ions of the two elements of the composite semiconductor.
最後に、本発明による装置の最良の性質は絶縁体の上に
シリコンを設ける技術(SilicOn−0n一1ns
u1at0rtechn010gy)によつて得られる
。Finally, the best feature of the device according to the invention is the silicon-on-insulator technology (SiliOn-0n-1ns).
ulat0rtechn010gy).
第1図は電荷移動の一方向性を得るために本発明により
一諸に使用される2個の半導体の異なる゛帯におけるエ
ネルギー分布を示す概略図である。FIG. 1 is a schematic diagram showing the energy distribution in different bands of two semiconductors used together according to the invention to obtain unidirectionality of charge transfer.
Claims (1)
と、1つの軸線に沿つて順次に配置され薄い絶縁層によ
り該基板から隔離されている金属電極の列と、少数キャ
リヤに対して上流端よりも下流端において大きい深さを
もつ非対称形の電位井戸を該基板の表面区域内につくり
かくして上記の軸線に沿つて該キャリヤの移動の一方向
性を得る手段と、少くとも最初の電極の下に少数キャリ
ヤを注入する手段と、少くとも最後の電極の下の電荷の
存在を検出する手段と、電圧源と、該電極を適当な値の
循環的に変化する電位とする少くとも1個の制御ライン
とを備え、上記の基板の表面区域内に非対称的な電位井
戸をつくり該キャリヤの移動の一方向性を得る手段は、
第1の半導体とは異なる禁止帯巾をもつ第2の半導体に
よつて形成され、該区域の1つの端で該基板内に位置し
た領域によつて構成され、前記2つの半導体の中の小さ
い禁止帯巾をもつ方の半導体は、上記の区域の下流に位
置している事を特徴とする電荷結合装置。1 a substrate constituted by a first doped semiconductor, an array of metal electrodes arranged sequentially along one axis and separated from the substrate by a thin insulating layer, and an upstream substrate for minority carriers; means for creating an asymmetrical potential well in the surface area of the substrate with a greater depth at the downstream end than at the end, thus obtaining unidirectionality of movement of the carrier along said axis; and at least the first electrode. means for injecting minority carriers under the at least one last electrode; means for detecting the presence of a charge under at least the last electrode; a voltage source; means for creating an asymmetrical potential well in the surface area of the substrate and obtaining unidirectionality of the carrier movement, comprising:
formed by a second semiconductor having a different bandgap than the first semiconductor, and constituted by a region located in the substrate at one end of the area; A charge-coupled device characterized in that the semiconductor having the forbidden band is located downstream of said zone.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7402410 | 1974-01-24 | ||
FR7402410A FR2259438B1 (en) | 1974-01-24 | 1974-01-24 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5129844A JPS5129844A (en) | 1976-03-13 |
JPS5921183B2 true JPS5921183B2 (en) | 1984-05-18 |
Family
ID=9133939
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50010383A Expired JPS5921183B2 (en) | 1974-01-24 | 1975-01-24 | charge coupled device |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPS5921183B2 (en) |
DE (1) | DE2502481A1 (en) |
FR (1) | FR2259438B1 (en) |
GB (1) | GB1467914A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6138821U (en) * | 1984-08-10 | 1986-03-11 | 住友電装株式会社 | clamp |
JPH0512129Y2 (en) * | 1986-05-09 | 1993-03-26 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0625967U (en) * | 1993-07-06 | 1994-04-08 | オムロン株式会社 | Coin slot structure |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4874190A (en) * | 1971-12-23 | 1973-10-05 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IE34899B1 (en) * | 1970-02-16 | 1975-09-17 | Western Electric Co | Improvements in or relating to semiconductor devices |
SE387186B (en) * | 1971-06-28 | 1976-08-30 | Western Electric Co | CHARGING COUPLED SEMICONDUCTOR DEVICE WITH DIFFERENT CHARGING CONCENTRATION ALONG THE INFORMATION CHANNEL |
-
1974
- 1974-01-24 FR FR7402410A patent/FR2259438B1/fr not_active Expired
-
1975
- 1975-01-14 GB GB160175A patent/GB1467914A/en not_active Expired
- 1975-01-22 DE DE19752502481 patent/DE2502481A1/en active Granted
- 1975-01-24 JP JP50010383A patent/JPS5921183B2/en not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4874190A (en) * | 1971-12-23 | 1973-10-05 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6138821U (en) * | 1984-08-10 | 1986-03-11 | 住友電装株式会社 | clamp |
JPH0512129Y2 (en) * | 1986-05-09 | 1993-03-26 |
Also Published As
Publication number | Publication date |
---|---|
DE2502481A1 (en) | 1975-07-31 |
GB1467914A (en) | 1977-03-23 |
FR2259438A1 (en) | 1975-08-22 |
FR2259438B1 (en) | 1976-10-08 |
DE2502481C2 (en) | 1989-04-20 |
JPS5129844A (en) | 1976-03-13 |
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