JPS59211283A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable to operate bistable oscillation in a high frequency with negative resistance in a simple circuit by providing a vertical negative resistor in an applied reverse high electric field by avalanche phenomenon in a semiconductor P-N junction. CONSTITUTION:Silicon semiconductor P-N junction surfaces are planely bonded, a negative resistor is provided between two parallel electrodes 4 and 5 provided in a P type semiconductor section, an electrode 6 is further provided to effectively produce the negative resistance. For example, two equal resistors R1 are connected in parallel between terminals 8 and 9, thereby obtaining characteristics of negative resistance existing in a vertical direction to the applied high electric field and negative resistance of oscillation, bistable state. As a current I generated by an avalanche phenomenon is increased in the P-N junction, the absolute value RN of negative resistance (-RN) is reduced, and when becoming the same value as the positive resistance RP, bistable state is produced, and the voltages of the terminals 8, 9 are positive or negative. When the current I further increases, the absolute value RN of the negative resistance (-R) becomes smaller than the positive resistance RP, and oscillation possible state is produced.

Description

[Detailed description of the invention] The present invention relates to a semiconductor device.

Most of the conventional I'I\1-fold, oscillation, and operation devices require the construction of complicated circuits, and their operating frequencies are not very high. The present invention addresses these shortcomings.

The present invention is a semiconductor device that has the disadvantage that when a reverse high electric field is applied to a semiconductor P, N junction, negative resistance occurs in a direction perpendicular to the applied high electric field due to an avalanche phenomenon.

Examples will be described below with reference to the drawings.

Figure 1 shows two parallel EWL4-5s provided in the P-type semiconductor part, with the junction surfaces of the Noricon semiconductor P and N junctions as planar junctions.
This is done so that there is a negative resistance between them. Furthermore, the electrode 6 is provided to more effectively generate negative resistance.

FIG. 2 shows an example of a circuit according to the embodiment described above, in which two equal resistors R+ are connected in parallel between terminals 8-9, resulting in a negative resistance and Characteristics due to negative resistance such as oscillation and bistable state are obtained.

Figure 3 shows the negative resistance (-1 (N)) that exists between terminals 8 and 9.
shows a positive resistance Rp existing in parallel with , and the action of both resistances is as shown below.

As the current ■ generated by the avalanche phenomenon in the P-N junction increases, the absolute value RN of the negative resistance (-R, N) decreases, and when it reaches the same value as the positive resistance Rp (RN = R, p), it becomes double. A stable state occurs and the voltage at terminals 8 and 9 assumes a positive or negative value. In this state, it can also function as a flip-flop by providing electrodes 12 and 13 as shown in FIG.

When the current ■ further increases, the absolute value R of the negative resistance (-RN)
N becomes smaller than the positive resistances R and p (RN<Rp), and a state in which oscillation is possible occurs.

In the above example, the avalanche occurred at E==78'V.

For the sample that starts with an electric current, R+=IKΩ, R2=a
When oon, E = 11.8'V, I = 5.3
m is 2.
5 Ill A increased to 4.4 mA. Furthermore, an oscillation state occurred at E=137 V, '=10.8 +n A, and an oscillation output of about 20 W, an efficiency of about 10%, and a maximum oscillation station e number of about 259 ME1z were obtained.

As described above, according to the present invention, operations such as bistable, oscillating, etc. due to color contrast can be performed at high frequencies with a conventionally simple circuit.

[Brief explanation of the drawing]

FIG. 1 is a perspective view of an embodiment, FIG. 2 is a circuit diagram of the embodiment, FIG. 3 is a relationship diagram between negative resistance and positive resistance, and FIG. 4 is an embodiment of a flip-flop. I P-type semiconductor portion, 2 N-type semiconductor portion, 3.
P-N junction boundary line, 4, 5, 6, 7, 12゜13
Electrode, 8, 9, 10, 11. ．． 14.15...terminal,
16・Power supply, R3, R2, R11, RN, Rp・Resistance.

Claims (1)

[Claims] A semiconductor device having a negative resistance in a direction perpendicular to an applied reverse high electric field due to an avalanche event at a semiconductor PN junction.