WO1987003426A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- WO1987003426A1 WO1987003426A1 PCT/JP1985/000659 JP8500659W WO8703426A1 WO 1987003426 A1 WO1987003426 A1 WO 1987003426A1 JP 8500659 W JP8500659 W JP 8500659W WO 8703426 A1 WO8703426 A1 WO 8703426A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- junction
- semiconductor
- negative
- effective mass
- carriers
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 230000002441 reversible effect Effects 0.000 claims abstract description 6
- 230000005684 electric field Effects 0.000 claims abstract description 5
- 230000004888 barrier function Effects 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000000969 carrier Substances 0.000 abstract description 6
- 230000003321 amplification Effects 0.000 abstract description 4
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 4
- 230000010355 oscillation Effects 0.000 abstract description 4
- 230000007704 transition Effects 0.000 abstract description 4
- 230000001133 acceleration Effects 0.000 abstract description 3
- 230000007850 degeneration Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
Definitions
- the present invention relates to an active semiconductor device having a negative resistance based on a negative effective mass of a carrier in a semiconductor.
- Devices using negative effective mass (lateral negative effective mass) based on the distortion of the wavenumber space energy surface existing in various directions have been considered.
- it is necessary to accelerate the carrier to the energy region where the negative effective mass exists.D it is not possible to be scattered by the grating before reaching the energy region. Is missing. Therefore, special conditions ** are required for the structure of the device and the temperature at which it is placed o (H. Kroemer: Proc. IRE. 47 (1959) P.393, Esaki and R. Tsu, IBM. Res. Develop 14 , 61 (1970)) Disclosure of the Invention
- the present invention is an active semiconductor device in which a carrier having a negative effective mass is obtained by a method different from such a method to obtain a negative resistance.
- a reverse reversible breakdown state of a junction having an energy barrier to a carrier in a semiconductor at about the degenerate temperature the carrier caused by the avalanche phenomenon is accelerated in the transition region of the junction. After going out of the transition area, the area around it! )scattering A high energy distribution state is formed in the wave number space in the region receiving much noise. In this state, the effective mass of the carriers (electrons and holes) becomes negative in the direction perpendicular to the applied accelerating electric field.
- bistable or oscillating state occurs between both ends of the resistance.
- FIG. 1 is a perspective view of a device having a preferred embodiment of the present invention.
- FIG. 2 is a basic circuit diagram using the device in FIG. 1 o
- FIG. 1 is a perspective view of a device having a preferred embodiment for carrying out the present invention.
- the junction in this device is a semiconductor PN plane junction, so the negative resistance occurs in a direction parallel to the junction plane.
- the active function based on this negative resistance is output to the outside by two electrodes 11 and 12 provided in the P-type semiconductor region 1 in this device.
- the electrodes 11 and 12 are designed to apply a reverse voltage to the junction together with the electrode 1 ′ 3 provided in the N-type semiconductor region 2.
- the area where these electrodes are provided can be reversed. Connecting to the device by configuring the electrodes in this way External circuits can be simplified and the high-speed operation inherent in the device can be utilized. Further, these electrodes 11 and 12 have a rectangular shape so that the negative resistance can be used efficiently, and the electrodes 11 and 12 are provided in parallel with each other.
- Fig. 2 is a basic circuit diagram using this device.
- the resistors and R connected to terminals 11 and 12 are equal in resistance according to the symmetry of the device.] Therefore, the output between terminals 11 and 12 is a balanced output. can get.
- the resistors connected in series to the terminals at terminals 13 are resistors for controlling the current I]
- E is the power supply.
- a negative resistance in the device as one R N, the positive resistance that exists in parallel therewith and R P, the operating state of the apparatus according to the magnitude of these two resistors by the following Uniruru .
- the absolute value of the negative resistance one R N
- R P R P
- the bistable state is established.
- a constant voltage is generated between terminals 11 and 12. This voltage increases as the current I increases, and this state is maintained as long as the average effective mass in the carrier's wave number space energy distribution state remains negative.
- the polarity of the voltage generated between terminals 11 and 12 can be controlled by providing an input electrode in one of the regions sandwiching the junction. .
- the input signal has an amplifying action. Therefore, in this state, it can be used as a bistable operation device or an amplification device. Furthermore, the current I reaches the increases state R N is Ru smaller R P I D (R N rather R P), the oscillation allowed between the terminals 1 1 and 1 2 Functioning. Therefore, in this state, it is possible to use as an oscillator by providing a capacitance and a reactance between the terminals 11 and 12 in series.
- the state in which the carrier has a negative effective mass utilizes the avalanche phenomenon of the carrier at the joint, and thus the structure, temperature, and the like are special. Require the following conditions. Therefore, it is expected to be used as an active device that can easily obtain high-speed operation, such as computation, amplification, and oscillation.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
An active semiconductor device having a negative resistance based upon a negative effective mass of carriers in a semiconductor. To obtain a negative resistance based upon a negative effective mass of carriers in the semiconductor, it is essential to accelerate the carriers to an energy region where there exists a negative effective mass to thereby form a condition that has a negative effective mass. When the junction having an energy barrier against the carriers in a semiconductor at about a degeneration temperature is in a reversibly broken down condition in the reverse direction, the carriers formed by the avalanche phenomenon are accelerated in the transition region of junction, go out of the transition region, and establish a wave-number space high-energy distribution condition having a negative effective mass in a direction perpendicular to the applied acceleration electric field in the surrounding regions. The negative resistance relying upon this condition can be directly obtained as output to produce such an active function as bistable amplification, oscillation or the like by providing an electrode in at least one of the two regions between which the junction is sandwiched. It is therefore expected that the device of this invention can be utilized as an active device to perform arithmetic operation, amplification, oscillation and the like at high speeds without any particular requirements with regard to the structure, temperature or the like.
Description
明 細 書 Specification
発明の名称 Title of invention
半 導 体 装 置 - 技 術 分 野 Semiconductor devices-technical field
この発明は、 半導体におけるキャ リ アの負有効質量に基づく負 抵抗を有する能動的半導体装置に関する。 The present invention relates to an active semiconductor device having a negative resistance based on a negative effective mass of a carrier in a semiconductor.
背 景 技 術 Background technology
半導体におけるキヤ リァの負有効質量を利用した能動的半導体 装置と して、 波数空間において印加加速電界に対し平行な方向に 存在する負有効質量（縦方向負有効質量）および印加加速電界に 対し垂直な方向に存在する波数空間エネルギー面の歪に基づく負 有効質量 (横方向負有効質量）を利用した装置が考えられている。 この二種の装置においては、 いずれもキャ リ アを負有効質量が存 在するェネルギー領域まで加速することが必要であ D、 そのエネ ルギー領域に達するまでに格子による散乱を受け いことが不可 欠である。 そのため装置の構造およびその置かれる温度等に特別 の条件か *'必要となる o (H.Kroemer:Proc. IRE. 47 (1959 )P.393, Esaki and R. Tsu, IBM. Res. Develop 14， 61 (1970 ) ) 発 明 の 開 示 As an active semiconductor device utilizing the carrier's negative effective mass in a semiconductor, the negative effective mass existing in the direction parallel to the applied acceleration electric field in the wavenumber space (longitudinal negative effective mass) and perpendicular to the applied acceleration electric field Devices using negative effective mass (lateral negative effective mass) based on the distortion of the wavenumber space energy surface existing in various directions have been considered. In both cases, it is necessary to accelerate the carrier to the energy region where the negative effective mass exists.D, it is not possible to be scattered by the grating before reaching the energy region. Is missing. Therefore, special conditions ** are required for the structure of the device and the temperature at which it is placed o (H. Kroemer: Proc. IRE. 47 (1959) P.393, Esaki and R. Tsu, IBM. Res. Develop 14 , 61 (1970)) Disclosure of the Invention
この発明は、 このようる方法とは異つた方法でキャ リ アが負有 効質量を持つ状態を起すことによ j?負抵抗を得るようにした能動 的半導体装置である。 一般に、 縮退温度程度の半導体におけるキ ャ リァに対するエネルギー障壁を持つ接合の逆方向可逆的絶緣破 壊状態においては、 雪崩現象によ ]?'生じたキャ リ アは接合の遷移 領域内で加速され、 遷移領域外へ出た後、 その近傍のあま！)散乱
を多く受け い領域で波数空間高エネルギー分布状態を形成する。 そしてこの状態にお ては、 キャ リ ア （電子および正孔）の有効 . 質量が、印加加速電界に対し垂直 方向に負とるる。 The present invention is an active semiconductor device in which a carrier having a negative effective mass is obtained by a method different from such a method to obtain a negative resistance. In general, in a reverse reversible breakdown state of a junction having an energy barrier to a carrier in a semiconductor at about the degenerate temperature, the carrier caused by the avalanche phenomenon is accelerated in the transition region of the junction. After going out of the transition area, the area around it! )scattering A high energy distribution state is formed in the wave number space in the region receiving much noise. In this state, the effective mass of the carriers (electrons and holes) becomes negative in the direction perpendicular to the applied accelerating electric field.
この状態に基づく負抵抗の絶対値がそれに並列に存在する正抵 抗の値と等しいかある はそれ以下の値のとき、 抵抗の両端間に おいて双安定または発振状態が生じる。 この二つの状態は、 接合 を挟む二つの領域のうち少くとも一方の領域に電極を設けること によ D外部に能動的機能と して直接出力することができる。 When the absolute value of the negative resistance based on this state is equal to or less than the value of the positive resistance existing in parallel with it, a bistable or oscillating state occurs between both ends of the resistance. These two states can be directly output as an active function to the outside of D by providing an electrode in at least one of the two regions sandwiching the junction.
図 面 の 簡 単 説 明 Brief explanation of drawings
第 1 図は、 この発明における好ま し 形態を有する装置の斜視 図である。 第 2図は、 第 1図における装置を使用した基本的回路 図である o FIG. 1 is a perspective view of a device having a preferred embodiment of the present invention. FIG. 2 is a basic circuit diagram using the device in FIG. 1 o
1〜 P型半導体、 2 型半導体、 3— P.N平面接合、 1 0…半導体装置、 1 1 , 1 2 , 1 3…電極、 1 to P-type semiconductor, 2-type semiconductor, 3-P.N planar junction, 10 ... Semiconductor device, 1 1, 1 2, 1 3 ...
, R5…抵抗、 E…電源、 I ···電流。 , R 5 ... resistance, E ... power supply, I · · · current.
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
第 1 図は、 この発明を実施するための好ましい形態を有する装 置の斜視図である。 図において、 この装置における接合は半導体 P - N平面接合で、 したがって負抵抗は接合面に平行な方向に生 じる。 この負抵抗に基づく能動的機能は、 この装置においては P 型半導体領域 1に設けられた 2個の電極 1 1および 1 2によって 外部に出力される。 また電極 1 1および 1 2は N型半導体領域 2 に設けられた電極 1 '3 と共に接合に逆方向電圧を印加するよ うに ¾つて る。 お、 これらの電極を設けた領域は逆にすることも 可能である。 このように電極を構成することによって装置に接続
される外部回路を簡単化し、 装置が本来有する高速の動作を生か すことができる。 また、 これらの電極 1 1および 1 2は負抵抗を 効率よ く利用できるように長方形状をし、 さらに電極 1 1および 1 2は互 に平行に設けられている。 FIG. 1 is a perspective view of a device having a preferred embodiment for carrying out the present invention. In the figure, the junction in this device is a semiconductor PN plane junction, so the negative resistance occurs in a direction parallel to the junction plane. The active function based on this negative resistance is output to the outside by two electrodes 11 and 12 provided in the P-type semiconductor region 1 in this device. The electrodes 11 and 12 are designed to apply a reverse voltage to the junction together with the electrode 1 ′ 3 provided in the N-type semiconductor region 2. The area where these electrodes are provided can be reversed. Connecting to the device by configuring the electrodes in this way External circuits can be simplified and the high-speed operation inherent in the device can be utilized. Further, these electrodes 11 and 12 have a rectangular shape so that the negative resistance can be used efficiently, and the electrodes 11 and 12 are provided in parallel with each other.
第 2図は、 この装置を使用した基本的な回路図である。 図にお て端子 1 1および 1 2に接続されて る抵抗 および R は、 装置の対称性に従って等しい抵抗値にしてあ ]?、 したがって端子 1 1 , 1 2間では出力は平衡出力と して得られる。 お、 装置に 直列に端子 1 3に接続されている抵抗 は電流 Iを制御するた めの抵抗であ ]?、 Eは電源である。 Fig. 2 is a basic circuit diagram using this device. In the figure, the resistors and R connected to terminals 11 and 12 are equal in resistance according to the symmetry of the device.] Therefore, the output between terminals 11 and 12 is a balanced output. can get. Note that the resistors connected in series to the terminals at terminals 13 are resistors for controlling the current I], and E is the power supply.
次に、 この装置における負抵抗を一 RN と し、 それに並列に存 在する正抵抗を RP とすると、 この二つの抵抗の大きさに従った 装置の動作状態は以下に示すよ うにるる。 接合の雪崩状態におけ る電流 Iが増加するに従って負抵抗（ 一 RN ) の絶対値は減少し. 正抵抗 RP と同じ値（ RN = RP )と ったとき、 双安定状態とな ϊ) , 端子 1 1および 1 2間に一定の電圧が生じる。 この電圧は、 電流 I の増加に従って増加し、 キヤ リ ァの波数空間エネルギ一分 布状態における有効質量の平均値が負の値を保つ間はこの状態は 維持される。 お、 この端子 1 1および 1 2間に生じた電圧は、 接合を挾む領域のいずれか一方の領域に入力用の電極を設けるこ とによ ]?外部からその極性を制御することができる。 また、 この 状態においては、 入力信号に対して増幅作用がある。 したがって この状態においては双安定演算装置あるいは増幅装置として利用 が可能である。 更に、 電流 Iが増加すると RN が RP よ D小さく る状態（ RNく RP ) に達し、 端子 1 1および 1 2間で発振可
能な状態と る。 したがつてこの状態においては、 端子 1 1およ び 1 2間にキャ パシタ ンスおよびリ アクタンスを '直列に設けるこ とによ ]?発振装置と しての利用が可能である。 Next, a negative resistance in the device as one R N, the positive resistance that exists in parallel therewith and R P, the operating state of the apparatus according to the magnitude of these two resistors by the following Uniruru . As the current I in the avalanche state of the junction increases, the absolute value of the negative resistance (one R N ) decreases. When the same value as the positive resistance R P (R N = R P ), the bistable state is established. Ϊ) A constant voltage is generated between terminals 11 and 12. This voltage increases as the current I increases, and this state is maintained as long as the average effective mass in the carrier's wave number space energy distribution state remains negative. The polarity of the voltage generated between terminals 11 and 12 can be controlled by providing an input electrode in one of the regions sandwiching the junction. . In this state, the input signal has an amplifying action. Therefore, in this state, it can be used as a bistable operation device or an amplification device. Furthermore, the current I reaches the increases state R N is Ru smaller R P I D (R N rather R P), the oscillation allowed between the terminals 1 1 and 1 2 Functioning. Therefore, in this state, it is possible to use as an oscillator by providing a capacitance and a reactance between the terminals 11 and 12 in series.
産業上の 利用可能性 Industrial applicability
以上に示したように、 この発明による装置にお ては、 キ ヤ リ ァが負有効質量を持つ状態は接合におけるキ ヤ リァの雪崩現象を 利用して るため、 その構造および温度等に特別の条件を必要と しるい。 したがって容易に高速動作が得られる演算、 増幅、 発振 等の能動的装置と して利用が期待される。
As described above, in the apparatus according to the present invention, the state in which the carrier has a negative effective mass utilizes the avalanche phenomenon of the carrier at the joint, and thus the structure, temperature, and the like are special. Require the following conditions. Therefore, it is expected to be used as an active device that can easily obtain high-speed operation, such as computation, amplification, and oscillation.
Claims
1. キ ヤ リ ァに対するエネルギー障壁を持つ半導体接合を構成し. 接合を挾む二つの領域のうち少く とも一方の領域に出力用の電極 を設け、 接合の逆方向絶緣破壊状態において、 雪崩現象によ ]?生 じたキ ヤ リァの印加加速電界に対し垂直 方向の負有効質量に基 づく負抵抗を有する半導体装置。 1. A semiconductor junction having an energy barrier to the carrier is constructed. An output electrode is provided in at least one of the two regions sandwiching the junction, and an avalanche phenomenon occurs when the junction is severely damaged in the reverse direction. A semiconductor device having a negative resistance based on a negative effective mass in a direction perpendicular to an applied accelerating electric field of the carrier.
2. 半導体がシリ コンである特許請求の範囲第 1項記載の半導体 2. The semiconductor according to claim 1, wherein the semiconductor is silicon.
3. 接合が半導体 p . N接合である特許請求の範囲第 1項又は第 2項記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the junction is a semiconductor pn junction.
4. 接合面が平面である特許請求の範囲第 1項ないし第 3項のい ずれかに記載の半導体装置。 4. The semiconductor device according to any one of claims 1 to 3, wherein the bonding surface is a flat surface.
5. 接合面の結晶方位が（ 1 1 1 ) である特許請求の範囲第 4項 記載の半導体装置。 5. The semiconductor device according to claim 4, wherein the crystal orientation of the bonding surface is (111).
6. 接合を挾む二つの領域のうち少く とも一方の領域に出力およ び逆方向電圧印加兼用の電極を 2個設けた特許請求の範囲第 1項 いし第 5項のいずれかに記載の半導体装置。 6. The method according to claim 1, wherein at least one of two regions sandwiching the junction is provided with two electrodes for both output and reverse voltage application. Semiconductor device.
7. 接合を挾む二つの領域のうち少く とも一方の領域に入力用の 電極を 2個設けた特許請求の範囲第 1項ないし第 6項のいずれか に記載の半導体装置。
7. The semiconductor device according to claim 1, wherein two input electrodes are provided in at least one of the two regions sandwiching the junction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP1985/000659 WO1987003426A1 (en) | 1985-11-28 | 1985-11-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP1985/000659 WO1987003426A1 (en) | 1985-11-28 | 1985-11-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1987003426A1 true WO1987003426A1 (en) | 1987-06-04 |
Family
ID=13846634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP1985/000659 WO1987003426A1 (en) | 1985-11-28 | 1985-11-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| WO (1) | WO1987003426A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5229636A (en) * | 1987-09-01 | 1993-07-20 | Tatsuji Masuda | Negative effective mass semiconductor device and circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4835776A (en) * | 1971-09-10 | 1973-05-26 | ||
| JPS59211283A (en) * | 1983-05-16 | 1984-11-30 | Tatsuji Masuda | Semiconductor device |
| JPS6049678A (en) * | 1983-08-26 | 1985-03-18 | Tatsuji Masuda | Semiconductor device |
-
1985
- 1985-11-28 WO PCT/JP1985/000659 patent/WO1987003426A1/en unknown
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4835776A (en) * | 1971-09-10 | 1973-05-26 | ||
| JPS59211283A (en) * | 1983-05-16 | 1984-11-30 | Tatsuji Masuda | Semiconductor device |
| JPS6049678A (en) * | 1983-08-26 | 1985-03-18 | Tatsuji Masuda | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5229636A (en) * | 1987-09-01 | 1993-07-20 | Tatsuji Masuda | Negative effective mass semiconductor device and circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US2801348A (en) | Semiconductor devices | |
| US6239638B1 (en) | SR flip flop | |
| US3098160A (en) | Field controlled avalanche semiconductive device | |
| US3226268A (en) | Semiconductor structures for microwave parametric amplifiers | |
| JP2576433B2 (en) | Protection circuit for semiconductor device | |
| US3792321A (en) | Piezoelectric semiconductor devices in which sound energy increases the breakdown voltage and power of capabilities | |
| JP3848479B2 (en) | Power semiconductor device manufacturing method | |
| WO1987003426A1 (en) | Semiconductor device | |
| US3173101A (en) | Monolithic two stage unipolar-bipolar semiconductor amplifier device | |
| US3675140A (en) | Acoustic wave amplifier having a coupled semiconductor layer | |
| US3691406A (en) | Surface acoustic wave generating system | |
| US3488527A (en) | Punch-through,microwave negativeresistance device | |
| JPH0560270B2 (en) | ||
| US5229636A (en) | Negative effective mass semiconductor device and circuit | |
| JPH0550149B2 (en) | ||
| US3339085A (en) | Four-layer pressure sensitive barrier type transducer device | |
| JPH03214780A (en) | High-frequency element | |
| US3518749A (en) | Method of making gunn-effect devices | |
| JPS59211283A (en) | Semiconductor device | |
| US3435303A (en) | Semiconductor bulk effect microwave oscillator | |
| JPS60259021A (en) | Logic circuit device | |
| US3327136A (en) | Variable gain tunneling | |
| JP2852046B2 (en) | Semiconductor device | |
| RU2245590C2 (en) | Semiconductor device having periodic electron-hole structure | |
| GB1114762A (en) | Improvements relating to microwave devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AK | Designated states |
Kind code of ref document: A1 Designated state(s): US |
|
| AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): DE FR GB |