JP2723521B2 - Latch circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latch circuit, and more particularly to a latch circuit that requires low-voltage operation in a reset state. [Prior Art] FIG. 2 shows an example of a conventional latch circuit. In the conventional latch circuit, the input terminal 1 is a set terminal, the input terminal 2 is a reset terminal, and the collector of the transistor Q100 is an output terminal 3.
It is composed of The operation of the circuit is such that the transistor Q100 is turned off when a thyristor (hereinafter, referred to as a thyristor) including the transistors Q2 and Q3 is operated, and the transistor Q100 is operated in a saturated state when the thyristor is turned off. Thus, the t ₁ as shown in FIG. 3, and the set terminal high level, the reset terminal the low level input, the thyristor transistor Q100 is cut off to work, the output terminal becomes a high level. After that, until the reset terminal becomes high level input,
The thyristor keeps operating and the output terminal keeps high level. With the reset terminal high level input, the thyristor is cut off, so that the transistor Q100 operates and the output terminal goes low. Thereafter, the thyristor keeps shutting down and the output terminal keeps keeping the low level until the set terminal goes high and the reset terminal goes low. [Problems to be Solved by the Invention] In the above-described latch circuit, the base potential VBQ100 (hereinafter referred to as VB100) of the transistor Q100 in the set state, that is, the thyristor operating state, is as shown in the following equation (1). However, V _BEQ2: NPN transistor Q2 base-emitter voltage V _CESatQ3: in the voltage thyristor operation state between the PNP transistor Q3 collector emitter, in order to shut off the Q _100, the V _B100 is V _B100 <V _BEQ100 (where V _BEQ100 is Therefore, _assuming that V _BEQ2 + V _CESatQ3 = 1V, the following equation (2) must be satisfied. On the other hand, in the thyristor cut-off state, the resistors R2, R100, and R101 need to satisfy the following equation (3) in order to operate the Q100 in the saturated state. V _CC = V _BEQ100 + I _R100 × (R2 + R100) I _R100 = I _BQ100 + V _BEQ100 / R101 I _CQ100 = (V _CC −V _CESat100 ) / R102 I _BQ100 = I _CQ100 / D Where h: Boltzmann's constant, q: elementary electron quantity, T: absolute temperature, I
_BQ100 : NPN transistor Q100 base current, I _CQ100 : Q100 collector current, V _BEQ100 : Q100 base-emitter voltage, V
_CESat Q100: Q100 collector-emitter saturation voltage, D: Q100 drive ratio, I _S : base-emitter reverse saturation current Furthermore, when using a latch circuit in an integrated circuit, PN
Since the current capability of the P transistor Q3 is limited, the resistance R
2 needs to be determined so as to satisfy the following equation (4). R2 ≧ V _CC / I _CMAX …… (4) where V _CC : power supply voltage maximum value, I _CMAX : PNP transistor Q
3Maximum collector current As described above, in the conventional latch circuit, (2),
The ratio of the resistors R2, R100, and R1001 must be set so that the expressions (3) and (4) hold. Therefore, the operation limit power supply voltage V in the reset state, that is, the thyristor cutoff state,
_CCMIN is expressed by the following equation (5). Therefore, if I _CMAX = 1mA, R2 = 5KΩ, R100 = 30KΩ, R1
001 = 15KΩ, V _BEQ100 = 0.5V, V _CESatQ100 = 0.1V, I _SQ100 =
The operating limit power supply voltage V _CCMIN in the reset state at 2.6 × 10 ^-16 A is V _CCMIN = _{1.93V according to} equation (5). In the case of the conventional circuit, when V _CC < _1.93V , as shown in FIG. in t _2, the reset terminal becomes high level, even if a reset state, the output transistor Q100 can not operate, the output terminal remains at a high level, will maintain the set state, poor voltage reduction characteristics There was a disadvantage. EXAMPLES Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention. In FIG. 1, when a high-level voltage is applied to an input terminal 1 (hereinafter referred to as a set terminal), an NPN transistor Q2 operates, and PNP transistors Q3 and Q4 are connected. Drive. Here, the circuit composed of Q2, Q3, R2, R3, R4 is a latch circuit, and even if the set terminal goes low after Q2, Q3, Q4 operates, Q2 is driven by Q3, so Q4 also operates. To maintain Q5 and Q6 to maintain operation
Is shut off, and the output terminal 3 becomes high level (t _{1 in} FIG. 3). Next, in the above-mentioned state, when a high-level voltage is applied to the input terminal 2 (hereinafter referred to as a reset terminal) and Q1 conducts and Q2 is cut off, Q3, Q4 and Q5 are cut off, so that Q6 conducts and the output becomes high. terminal becomes low level (Fig. 3t _2). Here, an operation limit power supply voltage (hereinafter, referred to as V _CC MIN) in a state where a high level voltage is applied to the reset terminal, that is, in a reset state, is represented by the following (6). Where k: Boltzmann's constant, q: electron quantity, T: absolute temperature, V
_BEQ6 : NPN transistor Q6 base-emitter voltage, I _BQ6 : Q
6 Base current, V _CESatQ6 : Q6 Collector-emitter voltage, I
_SQ6 : Reverse saturation current between Q6 base and emitter Therefore, if R6 = 35KΩ, R7 = _10KΩ , V _CESatQ5 = 0.1V, I
_SQ5 = 2.6 × 10 ^-16 operating limit supply voltage V _CCMIN the case of the A
Is V _CCMIN = 0.745V from the equation (6). [Effects of the Invention] As described above, in the present invention, in the reset state, that is, in the thyristor operating state, the output transistor Q6 is operated by the base potential self-bias, so that the operation limit power supply voltage is reduced. Operate to a low potential of 39% (in the case of the above example) of the latch circuit of FIG.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional example, FIG. 3 is a timing chart at the time of normal operation, and FIG. It is a timing chart at the time of abnormal operation. 1 ... input terminal 1 (set terminal) 2 ... input terminal 2
(Reset terminal), 3 ... Output terminal, 4 ... Stabilized voltage source, 5 ... Ground terminal, R0-R7 ... Resistance, Q0, Q2, Q3, Q4, Q5
…… NPN transistor, Q1, Q3 …… PNP transistor, S
... Set terminal input voltage level, R ... Reset terminal input voltage level, Q ... Output terminal voltage level.

Claims (1)

(57) [Claims] A first input terminal, a second input terminal, a collector connected to the first input terminal via a first resistor, a base connected to the second input terminal, and an emitter connected to the low potential side of the power supply. A first NPN transistor, a second NPN transistor having a base connected to the collector of the first NPN transistor, and an emitter connected to the low potential side of the power supply; a collector of the second NPN transistor; A second resistor connected in series with the potential side; a first resistor having an emitter connected to the intersection of the second and third resistors; and a collector connected to the base of the second NPN transistor. A PNP transistor and the first P
A fourth resistor connected between a base of the NP transistor and a collector of the second NPN transistor;
A second PNP transistor having an emitter connected to the intersection of the third resistor, a base of the second PNP transistor, a fifth resistor connected between the collector of the second NPN transistor, and the second PNP transistor; A sixth resistor connected between the collector of the PNP transistor and the low potential side of the power supply;
A third NPN transistor having a base connected to the collector of the second PNP transistor and an emitter connected to the low potential side of the power supply, and connected between the collector of the third NPN transistor and the high potential side of the power supply A seventh resistor, a base connected to the collector of the third NPN transistor, and a fourth NPN transistor connected to the emitter on the low potential side of the power supply; and a collector connected to the collector of the fourth NPN transistor and connected to the high power supply. An eighth resistor connected between the fourth NPN and the fourth NPN;
A latch circuit comprising an output terminal from a collector of a transistor.