JPS59210667A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59210667A JPS59210667A JP58085330A JP8533083A JPS59210667A JP S59210667 A JPS59210667 A JP S59210667A JP 58085330 A JP58085330 A JP 58085330A JP 8533083 A JP8533083 A JP 8533083A JP S59210667 A JPS59210667 A JP S59210667A
- Authority
- JP
- Japan
- Prior art keywords
- region
- wiring
- diffusion region
- type
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 229910000838 Al alloy Inorganic materials 0.000 claims description 7
- 239000013078 crystal Substances 0.000 abstract description 8
- 239000002244 precipitate Substances 0.000 abstract description 4
- 238000001556 precipitation Methods 0.000 abstract description 2
- 229910021364 Al-Si alloy Inorganic materials 0.000 abstract 2
- 108010053481 Antifreeze Proteins Proteins 0.000 abstract 1
- 229910045601 alloy Inorganic materials 0.000 description 13
- 239000000956 alloy Substances 0.000 description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 208000003251 Pruritus Diseases 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical group [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007803 itching Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は半導体装置の構造に係シ、特にシリコンを含む
アルミニウム合金配線の付設方法に関する０
（１））従来技術と問題点
半導体集積口＃（ＩＣ）笠の＃！：導体装政に於ては、
生導体ノー即ち機能領域に直に接する配線にシリコン（
Ｓｉ）を１〜２〔チ〕程度含んだアルミニウム（ＡＪ
）合金配線が多く用いられる。こｉｌは配線が形成され
た後に行われる表面気絶ｉ！ｌ１ｅＩの化学気相成長、
チップ・ボンディング、ケース刺止々、の工程に於て、
該配線が４００〜５００ ［：℃：］程既に昇温ぜしめ
られＩＣ際、Ａｌ配線に級している機能領域のＳｊがＡ
ｌ中に溶は込み、該機能領域の挫つ接合が破壊されるの
を防止するためで祝る。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to the structure of a semiconductor device, and particularly relates to a method for attaching aluminum alloy wiring containing silicon. (1) Prior art and problems Semiconductor integration port # (IC) Kasa's #! :In conductor arrangement,
No live conductors, i.e. silicon (
Aluminum (AJ) containing about 1 to 2 [Si]
) Alloy wiring is often used. This is the surface stunning i! that is done after the wiring is formed. chemical vapor deposition of l1eI,
In the process of chip bonding and case mounting,
When the wiring has already been heated to a temperature of 400 to 500 °C, the Sj of the functional area equivalent to Al wiring becomes A.
This is to prevent the melt from penetrating into the interior of the functional area and destroying the joints in the functional area.
しかし上記Ｓｔを含むＡ［合金配線を使用した場合には
、前記のように配線形城後に行われる加熱工程を経ると
、Ａｌ配線中に合金成分として含まれている常温に於て
過剰なＳｌが、該ｉ合金配置＋：’Ｊ Ｋ接するＳｉ層
即ち機能領域の表面に、Ａｌがドープされたｐ型のＳｔ
結晶となって析出する。However, in the case of using the above-mentioned St-containing A[alloy wiring, the heating process performed after the wiring is formed as described above will cause excess Sl contained in the Al wiring as an alloy component at room temperature. However, on the surface of the Si layer, that is, the functional region in contact with the i alloy arrangement +:
Precipitates as crystals.
そのため特にｎ型の機能領域から該Ａ［合金配線が導出
される場合には、該Ａ１合金配線に接するｎ型機能領域
面に析出した前記ｐ ｍ Ｓ ｉ結晶と該ｎ型機能領域
間にｌ） −ｎ接合が形成され該配線のコンタクト抵抗
が増大するという問題がある。Therefore, especially when the A[alloy wiring is derived from the n-type functional region, there is a l ) There is a problem in that a -n junction is formed and the contact resistance of the wiring increases.
そして第１図に上面図（イ）及び断面図（ロ）を示しだ
ように、％ ５博コ／タクト窓１内に表出するｎ型機能
領域２Ｆｎノから該電極コンタクト窓１を介して絶縁膜
３上に導出される前記Ａ４合金配線４に面積の大きいボ
ンアイツク・バッド５等が形成される」烏合にＩＣＥ
、’ｉＪＬ １Ｍコンタクト窓ｌ内に表出するｎ型機能
領域２ｉｆｉＪに特に該７バンデイング・パッド郁から
移動してきた多量のｐ型Ｓｉ結晶６が析出し、史１ｃ該
半柚体ＩＣが高密度高集積化され、電極コンタクト窓ｌ
が倣ｘ（ＩＩ化さｔした際には、該コンタクト；＆１内
に表出するｎ型威能狽Ｊ威２の全面をｐ型Ｓｉ結晶６が
キ立い、該Ａ１合金配線４が該ｎ型機能領域２に対して
非〃７通の状態になる。（図中、７はｐ型Ｓｔ凸仏、８
はフィールド酸化膜、９は薄い酸化膜）
（ｃ） 発明の目的
本発明は、配淡体にシリコンを含むアルミニウム合金を
用いる半導体装置に於て、該配δソ体中に含まれる／リ
コンが、電極コンタクト窓中に表出する４湿能領域上に
析出するの全抑ｆｌｉｌｌする記載、のイ」膜構造を提
供するものでりり、その目的とするところは上記問題点
を除去して半導体装を刊の性能及び信頒性を向上ぜしめ
るにある。As shown in the top view (a) and cross-sectional view (b) in FIG. A large area bond pad 5 etc. is formed on the A4 alloy wiring 4 led out on the insulating film 3.
, 'iJL 1M A large amount of p-type Si crystal 6, which has migrated from the 7 banding pads in particular, precipitates in the n-type functional region 2ifiJ exposed in the contact window 1, and the semi-silica IC has a high density. Highly integrated, electrode contact window
When the contact x (II) is formed, the p-type Si crystal 6 stands out over the entire surface of the n-type wire 2 exposed in the contact; &1, and the A1 alloy wiring 4 It becomes a non-7 state for the n-type functional region 2. (In the figure, 7 is a p-type St convex Buddha, 8
9 is a field oxide film, and 9 is a thin oxide film) (c) Object of the Invention The present invention provides a semiconductor device in which an aluminum alloy containing silicon is used as a thin body, in which silicon is contained in the thin body. The present invention provides a film structure that completely suppresses precipitation on the four moisture regions exposed in the electrode contact window, and its purpose is to eliminate the above-mentioned problems and improve semiconductor The aim is to improve the performance and credibility of the publication.
（ｄ） 発明のオｊ４成
即ち本発明は半導体装置に於て、第ｌの導電型を崩し素
子を構成する第１の拡散領域と、該第１の拡散領域に１
４接し、且つ該第１の拡散領域と分離されて配設された
第１導電型の第２の拡散領域とを有する第２導電型半導
体基根と、該半梼体基板上に配設され該第１の拡散領域
へ〇−第２の拡散領域面を個々に表出する第１及び第２
０開孔を竹する絶縁膜と、該第１の拡散領域面から該第
１の開孔を介して該絶縁膜上に導出され、ｉｌ； ２の
１］孔を介して該第２の拡散領域面に接し、且つ更に該
第２の開孔から該絶縁膜上に延在セ−しめらｉまたシリ
コンを含むｒルミニウム合金配線とをイｊしてなること
を特命とする。(d) The fourth aspect of the invention, that is, the present invention provides a semiconductor device with a first diffusion region that breaks the first conductivity type and constitutes an element, and a second diffusion region in the first diffusion region.
a second conductivity type semiconductor base having a second conductivity type second diffusion region which is in contact with the first conductivity type semiconductor substrate and which is arranged separately from the first diffusion region; To the first diffusion region 〇 - The first and second diffusion regions that individually expose the second diffusion region surface.
an insulating film having 0 apertures, and an insulating film led from the first diffusion region surface through the first apertures onto the insulating film; The special purpose is to form a wiring line that is in contact with the area surface and further extends from the second opening onto the insulating film and includes a silicon-containing aluminum alloy wiring line.
（ｅ） 発明の実施列
以下本発明を、ＭＯ８型半導体装置に於ける一実例につ
いて、絹２図に示す要部上面模式図（イ）及びそのＡ−
Ａ矢視断面図（ロ）を用いて詳細に説明する０
本発明を恥用したＭＯ８型半導体装置は、例えは第２図
（イ）及び（ｏ）に示すように、例えはｐ型シリコ／（
Ｓｌ）基Ｊ＆１１面にフィールド酸化膜１２及びその下
部のｐ′型チャネル・カット領域１３によってｆ＋１！
！１々の画定分離された第１の丞・板ｌｌ１１表出頭域
１４と第２の基板面表出領域１５とが隣接して設けらｔ
でおり、前記第１の基板面表出領域１４にイ５すえばゲ
ート八ツ化し１６．多結晶Ｓｔダグ−％−皮１７、ｎ＋
型ソース領域１８及びｎ十型ドレイン領域１９によって
構成されるｎチャネルＭＯＳトランジスタ（Ｔｒ ）が
、又第２の基板面表出領域１５釣ＶｔＳ屹しないｎ十型
ダミー拡散領域２０がそれぞれ形成されている。(e) Implementation of the Invention The present invention will be described below with reference to a schematic top view of the main part shown in Figure 2 (A) and its A-
The MO8 type semiconductor device using the present invention, which will be explained in detail using the sectional view (b) in the direction of arrow A, is made of p-type silicon, for example, as shown in FIGS. 2 (a) and (o). /(
The field oxide film 12 and the p'-type channel cut region 13 below it form f+1!
! The first substrate surface area 14 and the second substrate surface surface area 15 which are defined and separated from each other are provided adjacent to each other.
16. Then, if the first substrate surface exposed area 14 is formed into a gate 8, 16. Polycrystalline St Doug-%-Peel 17, n+
An n-channel MOS transistor (Tr) is formed by an n-type source region 18 and an n-type drain region 19, and an n-type dummy diffusion region 20 in which the voltage VtS does not exceed the second substrate surface exposed region 15 is formed, respectively. There is.
そして該基板上Ｋ例えばシん珪ばガラス（ＰＳＧ）よシ
なる絶縁膜２１が配設され、該絶縁膜２１に前記ソース
領域１８．ドレイン領域１９．ダミー拡散領域２０等を
それぞれ個々にプ・、出する第１゜第２．第３のコンタ
クト窓（ト；〕孔）２２ａ、２２ｂ。An insulating film 21 made of, for example, thin silicon glass (PSG) is disposed on the substrate, and the source region 18. Drain region 19. In the first and second stages, the dummy diffusion regions 20 and the like are individually pulled out. Third contact windows (holes) 22a, 22b.
２２ｃが設けられる。そして該絶ＲＪＩＮ２１上に、前
記第１のコンタクト窓２２ａを介してソース領域１８面
から導出された例えはＳｉを１〔俸〕程度含むＡ／−３
ｔ合金よりなる、ソース配線２３ ａ及び前記第２のコ
ンタクト窓２２ｂを介しドレイン領域１９１ｆｉ′ｉか
ら導出式ね、前記第３のコンタクト悪２２ｃケ弁してダ
ミー拡散領域２０面に接１、史に該第３のコンタクト窓
２２ｃ部から絶縁１１ｆｆｉ ２１上に延在し、先端部
に例えば１００〔μｍ〕角程度の広い面積を有するボン
アイツク・バッド２４がｔ配設された前記ＡＡ’−８ｉ
合金よりなるドレインＰ・）゛、訃、２３ｂが形成され
てなっている。22c is provided. Then, on the RJIN 21, for example, A/-3 containing about 1 [salt] of Si is drawn out from the surface of the source region 18 through the first contact window 22a.
The third contact layer 22c is connected to the surface of the dummy diffusion region 20 through the source wire 23a and the second contact window 22b, which is made of T-alloy, and is connected to the drain region 191fi'i. The AA'-8i is provided with a bond pad 24 extending from the third contact window 22c onto the insulation 11ffi 21 and having a large area of, for example, about 100 [μm] square at the tip.
A drain 23b made of an alloy is formed.
即ち該実施例に於ては、ｎ十型ドレイン領域１９からコ
ンタクト窓２２ｂを介して動、縁膜２１上にｍｌ出きれ
た先端部に広い面積のボンディング・・シノド２４を有
するＡｊ？−８ｉ合金ド１／イン配線２３ｂ伏、前記ド
レイン領域１９上のコンタクト窓２２ｂ型ダミー（ｊム
ｉ５ンＳ貢支、１Ｆ２０に手助り虫−？しめられている
。That is, in this embodiment, the Aj? -8i alloy dome/in wiring 23b on the side, contact window 22b type dummy on the drain region 19 (Jmui5inS contribution, 1F20 as a helper).
従って該１．１：Ｌ ）ｊ’ｊに於ては、該配痒刃ヒ成
が終った後に、デさ面保瞠絶札ミ膜（例えばカバーＰ
Ｓ Ｇ膜）の形成、チップ・ボンディング、ケース錆止
等の工杵に於て該Ａ／Ｌ Ｓｔ合金ドレイン配線が３５
０〜４５０［℃］８度の熱膣歴を経プ（際、大面積を有
するボンディング・・ノド部に含まれる多量のＳｔは主
２してコンタク） ’ｔｒｉ、 ２２ ｃ内に表出して
いるダミー拡散゛Ｅ・！１域２０上にｐルＶ、 Ｓ ｉ
結晶２５となって析出するので、コンタクト窓２２ｂに
於てｎ＋型トドレイン６化択１９上−ｖｒ出するｐ型−
８ｉ結晶２５のＭに極〈わずか（・ζなる。そのため該
：、Ｌ’： ＭＭｉ９１Ｊ ｉ′ζ−於て（伏、ボンデ
ィング・バンドを有するＡ／−８ｉ合金ドレイン配約２
３ ｂのドレイ／領域１９に対するコンタクト抵抗を、
ボンディング・バンド等大面積の゛ｉｆ１恥５を持たな
い例えはソース配縁２３ａのコンタクト抵抗と同等の低
い値に形成することがで、きた。Therefore, in the case of 1.1:L)j'j, after the formation of the itching blade is completed, the desa-men-ho-mu-zetsu-fuda-mi-membrane (for example, the cover P
The A/L St alloy drain wiring is
0 to 450 [℃] 8 degrees of heat vaginal history (when a large amount of St contained in the bonding throat area with a large area is mainly contact) 'tri, 22 c. Dummy spread゛E・! 1 area 20 above p le V, S i
Since the crystal 25 is precipitated, the p-type -vr which is emitted on the n+ type drain 6 formation option 19 in the contact window 22b
The M of the 8i crystal 25 has a very small amount of
The contact resistance for the drain/region 19 of 3b is
For example, a bonding band or the like which does not have a large-area "if1" can be formed to have a low value equivalent to the contact resistance of the source wiring 23a.
なお上記実施例に於ては、Ａｌ−８ｉ合金配糾とダミー
拡散領域との接触部（ダミー・３７２２１部）を、＃Ａ
ｌ−８ｉ合金配糾に於ける機能領域（ドレイン領域）と
のコンタクト部とボンディング・パッド部の間に１個所
設けたが、更に効果を大ならしめるために、ダミー・コ
ンタクト部を直列又は並列に２個所以上設けることもあ
る。このる合、ダミー拡散領域は１領域として形成して
共通に用いても良く、又個々に設けても良い０
父上記ダミー・コンタクト部を・設けることは、ボンデ
ィング・パッドを有する配線に限らず、］ノシ能領域か
ら絶縁膜上に長く娘出される配ぺに苅Ｕ。In the above example, the contact part (dummy 37221 part) between the Al-8i alloy and the dummy diffusion region was #A.
One contact is provided between the contact area with the functional area (drain area) and the bonding pad in the l-8i alloy arrangement, but in order to further enhance the effect, a dummy contact area is installed in series or parallel. There may be two or more locations. In this case, the dummy diffusion region may be formed as one region and used in common, or may be provided individually.The provision of the above-mentioned dummy contact portion is not limited to interconnects having bonding pads. , ] A long distance is placed on the insulating film from the noshi region.
ても上記同様の効果を生ずる。However, the same effect as above is produced.
＜ｆ）発明の詳細
な説明したように本発明によれは、半尋体装置の配線材
料にシリコンを含むアルミニウム合毎を用いる際、配線
形成後に与えられる熱負４Ｗｊによって配線中を移動し
てくるシリコンが、該配線と電気回路的に似能する領域
とのコンタクト部に達するのが抑止されるので、該コン
タクト部に析出するｐ詰ンリコン結晶の量は著しく減少
し、該シリコンを含むアルミニウム配線の該機能領域に
対するコンタクト抵抗は減少する０そしてこのコンタク
ト抵抗をｕ、゛り少ぜしめる効果はｎ型機能領域に対し
て特に−岩でイノる。<f) As described in detail of the invention, according to the present invention, when aluminum alloy containing silicon is used as the wiring material of a half-width body device, the aluminum alloy moves in the wiring due to the heat negative 4Wj applied after the wiring is formed. This prevents the silicon from reaching the contact area between the wiring and the region that functions like an electric circuit, so the amount of p-packed silicon crystals precipitated at the contact area is significantly reduced, and the aluminum containing the silicon The contact resistance of the wiring to the functional region is reduced by 0, and the effect of reducing this contact resistance by u is particularly pronounced for the n-type functional region.
従って本発明によｎば、シリコ／を含むアルミニウム合
金を配腺拐科として用いる半導体ＩＣの性能及び１よ軸
性を向上せしめることができる。Therefore, according to the present invention, it is possible to improve the performance and uniaxiality of a semiconductor IC using an aluminum alloy containing silico as a conductor.
第１図は従来の配線付設構造を示す上面図（勺及び断面
図（ロ）で、第２図はＭＯ８凋半導体装置に於ける本発
明の一実ｊｆｉＱ例を示す要部上面模式図（イ）及びそ
のＡ−Ａ矢俊１ｆｆｉ ＋＋’ｉｊ図（ロ）である。
図に於て、１１はｐ型シリコン基叔、１２はフィールド
ｒ？化１摸、１３はｐ″−型チャ不ル・カット領域、１
４は第１の基板面表出領域、１５は第２の基板面表出領
域、１６はゲート鈑化膜、１７は多結晶シリコ／・フー
ト電極、１８はｎ＋型ンース領域、１９はｎ＋＋ドレイ
ン領域、２０はｎ＋＋ダミー拡散領域、２１は絶縁膜、
２２ａ 、 ２２ｂ 、 ２２ｃ（７１−コンタクト窓
、２３ａはアルミニウムーフリ３フ合蛍ンース配憩、２
３ｂはアルミニウムーシリコン合金ドレイン配線、２４
はボンディング・バッド、２５は析出したｐ型シリコン
結晶を示す。Fig. 1 is a top view and cross-sectional view (b) showing a conventional wiring structure, and Fig. 2 is a schematic top view (Fig. ) and its A-A Yatoshi 1ffi ++'ij diagram (b). In the figure, 11 is a p-type silicon substrate, 12 is a field r?・Cut area, 1
4 is a first substrate surface exposed region, 15 is a second substrate surface exposed region, 16 is a gate plated film, 17 is a polycrystalline silicon foot electrode, 18 is an n+ type source region, and 19 is an n++ drain 20 is an n++ dummy diffusion region, 21 is an insulating film,
22a, 22b, 22c (71-contact window, 23a is aluminum free 3-piece fluorescent distribution, 2
3b is aluminum-silicon alloy drain wiring, 24
25 indicates a bonding pad, and 25 indicates a deposited p-type silicon crystal.
Claims (1)
該第１の拡散領域に隣接し２、且つ該第１の拡散領域と
分離されて配設された第１導電型の第２の拡散領域とを
有する第２導電型半導体基板と、該半導体基枦上に配設
され該第１の拡散領域及び第２の拡散領域面を個々に表
出する第１及び第２の開孔を有する絶縁膜と、該第１の
拡散領域面から該第１の開孔を介して該絶縁膜上に導出
され、該第２の開孔を介し２て該第２の拡散領域面に１
妾１７、且つ更に該第２の開孔から該絶縁膜上に延在せ
しめられたシリコンを含むアルミニウム合金配線とを有
してなることを特徴とする半導体装置。a first diffusion region having a first conductivity type and forming an element;
a second conductivity type semiconductor substrate having a second conductivity type second diffusion region adjacent to the first diffusion region and separated from the first diffusion region; an insulating film having first and second apertures disposed on the bridge and exposing the first diffusion region and the second diffusion region respectively; 2 is led out onto the insulating film through the opening, and 1 is led out onto the second diffusion region surface through the second opening.
A semiconductor device characterized in that it has a concubine 17 and further an aluminum alloy wiring containing silicon extending from the second opening onto the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58085330A JPS59210667A (en) | 1983-05-16 | 1983-05-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58085330A JPS59210667A (en) | 1983-05-16 | 1983-05-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59210667A true JPS59210667A (en) | 1984-11-29 |
| JPH0362025B2 JPH0362025B2 (en) | 1991-09-24 |
Family
ID=13855620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58085330A Granted JPS59210667A (en) | 1983-05-16 | 1983-05-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59210667A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6278878A (en) * | 1985-10-01 | 1987-04-11 | Mitsubishi Electric Corp | Semiconductor device |
| WO1992007380A1 (en) * | 1990-10-15 | 1992-04-30 | Seiko Epson Corporation | Semiconductor device having switching circuit to be switched by light and its fabrication process |
| JP2015185793A (en) * | 2014-03-26 | 2015-10-22 | 株式会社豊田中央研究所 | semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4875169A (en) * | 1972-01-12 | 1973-10-09 |
-
1983
- 1983-05-16 JP JP58085330A patent/JPS59210667A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4875169A (en) * | 1972-01-12 | 1973-10-09 |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6278878A (en) * | 1985-10-01 | 1987-04-11 | Mitsubishi Electric Corp | Semiconductor device |
| WO1992007380A1 (en) * | 1990-10-15 | 1992-04-30 | Seiko Epson Corporation | Semiconductor device having switching circuit to be switched by light and its fabrication process |
| JP2015185793A (en) * | 2014-03-26 | 2015-10-22 | 株式会社豊田中央研究所 | semiconductor device |
| US9437700B2 (en) | 2014-03-26 | 2016-09-06 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0362025B2 (en) | 1991-09-24 |
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