JPS60117771A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60117771A JPS60117771A JP22745483A JP22745483A JPS60117771A JP S60117771 A JPS60117771 A JP S60117771A JP 22745483 A JP22745483 A JP 22745483A JP 22745483 A JP22745483 A JP 22745483A JP S60117771 A JPS60117771 A JP S60117771A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- contact
- aluminum
- type region
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 239000000758 substrate Substances 0.000 abstract description 9
- 229910021364 Al-Si alloy Inorganic materials 0.000 abstract 3
- 229910000676 Si alloy Inorganic materials 0.000 description 10
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 10
- 230000004888 barrier function Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は半導体装置、特に上面に延在するアルミニウム
またはアルミニウム合金からなる配線層の改善された構
造に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device, and more particularly to an improved structure of a wiring layer made of aluminum or an aluminum alloy extending over the top surface.
fbl 従来技術と問題点
周知のように半導体集積回路(IC)などの半導体装置
においては、半導体基板面に半導体素子やその他の素子
が形成され、これから導出する配線はアルミニウム(A
I)またはアルミニウム合金が用いられる。アルミニウ
ム合金といっても他金属は僅かに数%(10%以下)を
含んだアルミニウムが主体の合金であるが、このように
アルミニウムが配線として利用される理由は電気的抵抗
が低く、絶縁膜との接着力が強くて、安価に得られ、し
かも形成が容易であるためである。fbl Prior Art and Problems As is well known, in semiconductor devices such as semiconductor integrated circuits (ICs), semiconductor elements and other elements are formed on the surface of a semiconductor substrate, and the wiring derived from these is made of aluminum (A
I) or aluminum alloys are used. Although it is called an aluminum alloy, it is mainly made of aluminum containing only a few percent (10% or less) of other metals.The reason why aluminum is used for wiring is that it has a low electrical resistance and is suitable for insulating films. This is because it has strong adhesive strength, is inexpensive, and is easy to form.
しかしながら、アルミニウムは製造工程中の熱処理又は
使用中の温度上昇によって、接触しているシリコン基板
と反応し、シリコンエピタキシャル層を接触面にエピタ
キシャル成長する問題がある。特に、アルミニウムシリ
コン合金の場合はエピタキシャル成長が顕著に起こり、
これはアルミニウムに含まれるシリコンが核になって成
長する−ものと考えられている。しかし、一般に詳しい
メカニズムは定かではない。また、エピタキシャル成長
が起こるのは、アルミニウムシリコン合金に限られず、
純アルミニウム配線にも見られている。However, there is a problem in that aluminum reacts with the silicon substrate it is in contact with due to heat treatment during the manufacturing process or temperature increase during use, and a silicon epitaxial layer is epitaxially grown on the contact surface. In particular, in the case of aluminum-silicon alloys, epitaxial growth occurs significantly,
This is thought to occur because silicon contained in aluminum serves as a nucleus for growth. However, the detailed mechanism is generally not clear. In addition, epitaxial growth is not limited to aluminum silicon alloys.
It is also seen in pure aluminum wiring.
ところで、このようにして成長するエピタキシャル成長
層は本来のシリコン基板とは異なる性質のシリコン層と
なって接触抵抗が大きくなり、コンタクト障害を生じる
。第1図は従来例の断面図を示しており、1はP型シリ
コン基板、2はN+型領領域3.4はアルミニウムシリ
コン合金配線で、5がコンタクト障害となるエピタキシ
ャル成長層である。本例では、電源Vと接続し、且つ配
線層が長い側のアルミニウムシリコン合金配線4の接触
部分にアルミニウムを含んだP型エピタキシャル成長N
5が顕著に成長している。この場合はN+型領領域2の
接触によりPN接合ができるため、接触抵抗は特に大き
くなる。Incidentally, the epitaxial growth layer grown in this manner becomes a silicon layer with properties different from those of the original silicon substrate, resulting in increased contact resistance and contact failure. FIG. 1 shows a cross-sectional view of a conventional example, in which 1 is a P-type silicon substrate, 2 is an N+ type region 3, 4 is an aluminum-silicon alloy wiring, and 5 is an epitaxial growth layer that becomes a contact barrier. In this example, P-type epitaxial growth N containing aluminum is connected to the power supply V and is connected to the contact portion of the aluminum-silicon alloy wiring 4 on the side where the wiring layer is long.
5 has grown significantly. In this case, a PN junction is formed due to the contact of the N+ type region 2, so that the contact resistance becomes particularly large.
このようなエピタキシャル成長層の形成は、ただ単に接
触抵抗の増大のみならずに半導体素子の特性をも劣化さ
せる。例えば、バイポーラトランジスタのエミッタ電圧
を劣化させることも知られている。Formation of such an epitaxial growth layer not only increases the contact resistance but also deteriorates the characteristics of the semiconductor element. For example, it is also known to degrade the emitter voltage of bipolar transistors.
従って、従来よりその対策が考えられて、例えば他の材
料膜(高融点金属窒化膜など)をバリヤ層として接触面
に介在させる方法が提案されている。しかし、バリヤ層
はアルミニウム膜のように低抵抗ではないから、ある程
度の接触抵抗の増加となり、決して好ましいとは云えな
い。Therefore, countermeasures against this problem have been considered and, for example, a method has been proposed in which a film of another material (such as a high melting point metal nitride film) is interposed as a barrier layer on the contact surface. However, since the barrier layer does not have a low resistance like an aluminum film, the contact resistance increases to some extent, which is by no means preferable.
(C) 発明の目的
本発明は、このようなアルミニウムまたはアルミニウム
合金膜からなる配線のオーミックコンタクト障害を防止
する新規な配線構造を提案するものである。(C) Object of the Invention The present invention proposes a novel wiring structure that prevents such ohmic contact failures in wiring made of aluminum or aluminum alloy films.
(d) 発明の構成
その目的は、素子電極がら導出するアルミニウム配線ま
たはアルミニウム合金配線が、該素子電極の近くで、該
素子電極の接続面積より大きな接続面積を有するダミー
コンタクト電極が設けられて延在する半導体装置によっ
て達成される。(d) Structure of the Invention The object of the invention is to extend the aluminum wiring or aluminum alloy wiring led out from the element electrode by providing a dummy contact electrode having a larger connection area than the connection area of the element electrode near the element electrode. This is achieved by existing semiconductor devices.
te) 発明の実施例 以下2図面を参照して実施例によって詳細に説明する。te) Examples of the invention Examples will be described in detail below with reference to two drawings.
第2図は本発明にががる一実施例の平面図を示し、第3
図は同図のAA断面図である。図において、P型シリコ
ン基板1に抵抗素子としてのN+型領領域2設けられて
おり、このN+型領領域ら接続電極2Dを通してアルミ
ニウムシリコン合金配線3.14が導出されているが、
電源■と接続し、且つ配線層が長い方のアルミニウムシ
リコン合金配線14は、シリコン基板面に設けた電気的
絶縁領域、即ちN+型領領域12接触して導出されてい
る。尚、10は二酸化シリコン膜からなる絶縁膜を示し
ており、配線層は幅2μm、厚さ1μm程度のもので、
N+型領領域2の接続電極2Dは1.5μmφである。FIG. 2 shows a plan view of an embodiment according to the present invention, and FIG.
The figure is a sectional view taken along line AA in the figure. In the figure, an N+ type region 2 as a resistance element is provided on a P type silicon substrate 1, and an aluminum silicon alloy wiring 3.14 is led out from this N+ type region through a connection electrode 2D.
The aluminum-silicon alloy wiring 14 connected to the power source (1) and having a longer wiring layer is led out in contact with an electrically insulating region, that is, an N+ type region 12 provided on the silicon substrate surface. Note that 10 indicates an insulating film made of a silicon dioxide film, and the wiring layer has a width of about 2 μm and a thickness of about 1 μm.
The connection electrode 2D of the N+ type region 2 has a diameter of 1.5 μm.
このような構造にして、接続電極の近傍に設けたN+型
領領域12アルミニウムシリコン合金配線14との接触
電極14D(ダミーコンタクト電極)の面積を接続電極
2Dの面積より十分大きくすれば、接続電極2Dにおけ
るエピタキシャル成長が著しく抑制されて、コンタクト
不良障害が防止される。With this structure, if the area of the contact electrode 14D (dummy contact electrode) with the N+ type region 12 aluminum silicon alloy wiring 14 provided near the connection electrode is made sufficiently larger than the area of the connection electrode 2D, the connection electrode Epitaxial growth in 2D is significantly suppressed and contact failure failures are prevented.
上記はN+型領領域ら電源■に接続するアルミニウムシ
リコン合金配線層の実施例であるが、その他の実験結果
によれば必ずしもN+型領領域接続する配線、または電
源に接続する配線のみならず、通常の配線、特に配線長
を長(導出する配線にもコンタクト障害が生じており、
その場合にも本発明を適用して同様の効果を得られるこ
とが判明した。The above is an example of an aluminum-silicon alloy wiring layer connecting the N+ type region to the power supply (2), but other experimental results show that not only the wiring connecting the N+ type region or the wiring connecting to the power supply Normal wiring, especially long wiring length (contact failure also occurs in the wiring to be derived,
It has been found that the same effect can be obtained by applying the present invention in that case as well.
ff) 発明の効果
以上の説明から明らかなように、本発明によればアルミ
ニウムまたはアルミニウムシリコン合金からなる配線を
バリヤ層を設けることなく、言い換えれば接触抵抗を増
加することなく、コンタクト障害から半導体装置を守る
ことができるから、高信頼化され、且つ高性能化された
半導体装置が得られるものである。ff) Effects of the Invention As is clear from the above description, according to the present invention, wiring made of aluminum or aluminum-silicon alloy can be used in semiconductor devices from contact failure without providing a barrier layer, or in other words, without increasing contact resistance. Since it is possible to protect the semiconductor device, a highly reliable and high-performance semiconductor device can be obtained.
第1図は従来例の構造断面図、第2図は本発明にがかる
一実施例の平面図、第3図は同図のAA断面図である。
図中、1はP型シリコン基板、2はN+型領領域抵抗素
子)、3,4.14はアルミニウムシリコン合金配線、
5はコンタクト障害となるエピタキシャル成長層、10
は絶縁膜、12は電気的絶縁領域(N+型領領域、2D
は接続電極、14Dは配線14とのダミーコンタクト電
極を示している。FIG. 1 is a structural sectional view of a conventional example, FIG. 2 is a plan view of an embodiment according to the present invention, and FIG. 3 is a sectional view along line AA of the same figure. In the figure, 1 is a P-type silicon substrate, 2 is an N+ type region resistance element), 3, 4.14 is an aluminum silicon alloy wiring,
5 is an epitaxial growth layer that becomes a contact obstacle; 10
is an insulating film, 12 is an electrically insulating region (N+ type region, 2D
indicates a connection electrode, and 14D indicates a dummy contact electrode with the wiring 14.
Claims (1)
ウム合金配線が、該素子電極の近くで、該素子電極の接
続面積より大きな接続面積を有するダミーコンタクト電
極が設けられて延在することを特徴とする半導体装置。A semiconductor device characterized in that an aluminum wiring or an aluminum alloy wiring led out from an element electrode extends near the element electrode with a dummy contact electrode having a connection area larger than the connection area of the element electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22745483A JPS60117771A (en) | 1983-11-30 | 1983-11-30 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22745483A JPS60117771A (en) | 1983-11-30 | 1983-11-30 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60117771A true JPS60117771A (en) | 1985-06-25 |
Family
ID=16861118
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22745483A Pending JPS60117771A (en) | 1983-11-30 | 1983-11-30 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60117771A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5994780A (en) * | 1997-12-16 | 1999-11-30 | Advanced Micro Devices, Inc. | Semiconductor device with multiple contact sizes |
JP2015185793A (en) * | 2014-03-26 | 2015-10-22 | 株式会社豊田中央研究所 | semiconductor device |
JP2018125443A (en) * | 2017-02-01 | 2018-08-09 | トヨタ自動車株式会社 | Semiconductor device |
-
1983
- 1983-11-30 JP JP22745483A patent/JPS60117771A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5994780A (en) * | 1997-12-16 | 1999-11-30 | Advanced Micro Devices, Inc. | Semiconductor device with multiple contact sizes |
US6211058B1 (en) | 1997-12-16 | 2001-04-03 | Advanced Micro Devices, Inc. | Semiconductor device with multiple contact sizes |
JP2015185793A (en) * | 2014-03-26 | 2015-10-22 | 株式会社豊田中央研究所 | semiconductor device |
US9437700B2 (en) | 2014-03-26 | 2016-09-06 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Semiconductor device |
JP2018125443A (en) * | 2017-02-01 | 2018-08-09 | トヨタ自動車株式会社 | Semiconductor device |
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