JPS59208884A - Manufacture of buried method type semiconductor laser element - Google Patents

Abstract

PURPOSE:To improve the wetting property of solder at the time of mounting the titled element by flatterning the surface on the side of a multilayer structure by a method wherein a growth promoting layer wherein a GaAs layer grows also at the stripe part is previously provided on a P type clad layer, when the GaAs layer is grown by lamination on a buried layer. CONSTITUTION:An N type GaAlAs clad layer 5, a GaAs active layer 6, a P type Ga1-xAlxAs clad layer 7, and the Ga1-yAly As growth promoting layer 15 are laminated on a GaAs substrate 2. Many mesa etching grooves 16 are provided in parallel in the fixed direction, the P type GaAlAs buried layers 4 are grown, and a GaAs or Ga1-zAlzAs flattened layer 17 is grown. At this time, setting the mixed crystal ratio (y) of the Al of the growth promoting layer 15 at zero causes the buried layer 4 to grow on said layer 15, increasing the ratio (y) does not cause the flattened layer 17 on said layer 15, keeping the ratio (y) at approx. 0.01-0.2 causes said layer 17 also on said layer 15.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a buried hetero semiconductor laser device.

As a semiconductor laser (laser diode), Ga
Visible lasers made from the AtAS system (non-government lasers) or long wavelength lasers made from the InGaAsP system are known. In addition, as one structure of the semiconductor laser X-ray, a buried hetero
A semiconductor laser device of the type [hetero 5 structure] is known. Figure 1 shows the simplest structure of BH semiconductor laser devices, such as J, Appl, Phys.

45.11.4899. This is an addendum published in '74.

Bl)1 Semiconductor laser crystal structure is GaA tA s
The InGaAsP system and the InGaAsP system have approximately the same structure. The figure shows a GaAzAs-based BH semiconductor laser device (hereinafter also simply referred to as a chip).

Semiconductor laser device (chip) III type (JaAs
It is formed based on a substrate 2, has a striped double heterojunction structure (stripe part) 3 in the center, and both f411 of this double heterojunction structure 3 are made of high resistivity p
The structure is covered with a buried layer 4 made of GaAzAs. To form this structure, Q
Moon-shaped cladding layer 5 consisting of a A IA s , Ga
Active M 6 consisting of As, p consisting of C4aAtAs
After sequentially forming the shaped rad layers 7, a pair of grooves are formed parallel to each other by etching to form a striped double heterojunction structure (stripe portion) 3. Shape/A.

Thereafter, high resistivity p-type Ga AzA s
The embedded layer 4 made of the above is shaped to form a buried heterojunction.

Next, using the insulating film (Sin2 film) 8 as a mask, Zn is diffused into the p-type rad layer 7 (diffusion regions are dotted in the figure) to form a contact layer. Then, the @pole 9 made of Cr and Au is provided on the main surface trill, and the lower mK of the Ga A sM plate 2 on the opposite surface is provided.
An electrode 10 made of AuGe1'li, Cr, and Au is provided, and a chip 1 is obtained by performing interosseous separation and division.

By the way, in this BH chip 1, due to the formation of a double-terror when the shape of the buried layer 4 is formed, a double
The growth of Hll becomes faster, and the inner layer 1 of the buried layer 4. The side is mounded, and the stripe part and 11)]
A level difference of about 5 μrn will occur.

As a result, as shown in FIG. 2, if it is fixed to the submount 12 via the solder 11 in the P side down state, will it be a tsuruter? It is the inventor's responsibility to avoid the occurrence of embarrassing problems. The existence of this cavity 13 increases the thermal resistance, resulting in heat generation, an increase in operating current, and the transmission of heat, which causes deterioration.

The inventor also focused on reducing the contact resistance of the P-side electrode 9. B of QaAlAs system
The contact with the P(l]11% pole of the i-t chip is a GaAtAs layer. Also, the contact resistance of (f4aAtAs) is three times thicker than that of 1dGaAs.

Therefore, the present inventor has created this ()a A s fg P 1
1i]'Used as a contact layer in the M pole
We considered planarizing the electrode portion (2) by growing an aAs layer (2) on the stripe portion and the buried layer.

However, the uppermost p-type rad layer 7 of the double hesozoelectric junction structure is made of Ga, -xAZxAs, and At, which is easily oxidized.
The mixed crystal ratio X used is, for example, about x = 0.3 to 0.35. This iζ, (J a A I A s
Oa The s-layer does not grow.

Therefore, the present inventors stacked Ga on the front b14 buried layer 4.
When each layer of A is grown, Q a A also occurs in the stripe part.
The present invention was developed with the idea that by providing in advance on the P cladding layer 7 a layer that can be called a growth promotion layer that causes the growth of the S layer, the G a A S layer can also grow above the stripe portion. .

Therefore, it is an object of the present invention to provide a method for manufacturing a BH peninsular laser device, which improves the turbidity of solder during device mounting by flattening the surface of the multilayer structure side of the BH half-center laser device. It's about doing.

Another object of the present invention is to provide a method for manufacturing a BH semi-integrated leather component which can reduce the contact resistance on the multilayer structure side of the BH half integrated leather component. .

The present invention will be explained below with reference to examples.

FIGS. 3(a) to 3(e) show B11 according to an embodiment of the present invention.
1 is a cross-sectional view showing the manufacturing method of a semi-coated laser element, and FIG.

The BH semiconductor laser device (13i-1 chip) of this embodiment is manufactured by the procedure shown in FIGS. 3(a) to <e>.

As shown in the figure (a), a semiconductor thin plate (wafer) 14 consisting of four n-type UaAs plates 2 with a thickness of about 100 μm is shown.
After preparing, a four-layer multilayer structure is formed by a commonly used liquid phase epitaxial moxibustion method. ′1, that is, G a
A moon-shaped cladding layer 5 made of GaAAAS with a thickness of about 1.5 μm and containing 1゛e and becoming n-type is provided on the A s , -I+¥ plate 2, and on top of this a moon-shaped cladding layer 5 made of GaAAAS is provided. An active layer 6 with a thickness of about 0.1 to 0.2 μm, a p-type layer 6 containing Zn and a thickness of about 2.0 μm (J a 1-
P-shaped rad layer 7 consisting of x A Z x A s.
A growth promoting layer 15 made of Ga, -, and AtyAs and having a thickness of about 0.5 .mu.xn is formed. Since the growth promoting layer 15 is a region in which Zn is diffused in a later step and becomes p-type, it may be of either the n-type or p-type, which is a quadrielectric type, during epitaxial growth. In this step, regions of different conductivity types are formed above and below the active layer 6, resulting in a double heterojunction structure 3. Further, the At mixed crystal ratio X of the p-type rad layer 7 is usually 0,
It is about 3 to 0.35. Furthermore, At of the growth promoting layer 15
Although the mixed crystal ratio y is not zero, it is an extremely small value, and a fake is effective, for example, by about 0.01 to 0.2.

Next, as shown in the figure), a large number of mesa etches 7416 are provided in parallel in a predetermined direction to form striped portions 3 at regular intervals. Mesa etching is made to reach the GaAs substrate 2. Further, the width of the active layer 6 is approximately 2 μm.

Next, as shown in FIG. 3C, a p-type buried layer 4 made of GaAtAs containing Zn is grown in the mesa etched groove 16 by liquid phase epitaxial growth. Then, when the buried layer 4 reaches the surface (upper end) of the growth promoting layer 15, a flattening layer 17 of n-type GaAs containing Ten or a Ga, -z AZ z As empty layer 17 is grown, for example. It is formed to a thickness of about 0.5 μn1. The planarization layer 17 is made of GaAt with high contact resistance because it becomes a contact layer with the electrode.
As j '), Oa As is also more desirable. Therefore, the planarization layer 17 is made of QaAs or Ga 1 + z A
Also for tzA s, a value smaller than the At mixed crystal ratio Z9i value is selected.

On the other hand, if the At mixed crystal ratio y of the growth promoting layer 15 in 1JIJ is set to zero and GaAs, then the p-type GaAtAS constituting the buried layer 4 will simultaneously grow on the growth promoting layer 15 during the growth of the buried layer 4. Because of this growth, it becomes impossible to achieve the intended purpose of flattening the multi-layered side surface of the chip. Therefore, the mixed crystal ratio y of A4 in the growth promoting layer 15 often cannot be set to zero.

Furthermore, if the value of y is increased, no matter how much the planarizing layer 17 is grown on the buried 1@4, it will not grow on the growth promoting layer 15. Therefore, as mentioned above, change the value of y from 0.01 to
When the value is set to about 0.2, the planarizing layer 17 starts to grow on the growth promoting layer 15 as well.

This value of y was determined by the inventor through experiments,
The upper and lower limits are not limited to these, but can be estimated to be approximately between these species.

Furthermore, when the buried layer 4 reaches the upper end of the growth promoting layer 15, the operation of changing the growth of the flattening layer 17 is performed between the upper surface of the growth promoting layer 15 and the portion where the top of the buried layer 4 is raised. This is because the planarization layer 17 is grown before a step is formed on the surface of the chip, and the surface corresponding to the stripe portion 3 of the chip and the regions on both sides of the chip are planarized.

In addition, the planarization layer 17 is made n-type because, if current confinement is performed using an insulating film, steps will be created due to the insulating film, and the planarization of the chip surface will be impaired. This is to create a reverse bias between the p-type buried layer 4 and the p-type buried layer 4.

Therefore, in a chip in which the GaAs layer plate is p-type, this flattening layer 4 is p-type.

Next, as shown in Figure (d), Zn was diffused in a stripe pattern in the middle of the P-shaped rad pigeon 7 using a commonly used photoetching technique (two dots were applied on the ridge). Ru.

) to form a contact layer. Thereafter, the mask used during photoetching is removed, and Cr is deposited on the planarization layer 17.
, a p-type electric field 9 made of Au is formed, and the wafer 14 is
Au (jeN i, Cr.

An n-type electrode 1o made of Au is formed.

Next, an external force is applied to the wafer 14, and the wafer 14 is folded in the open direction, and the wafer 14 is divided at the center of the implantation dovetail 4, as shown in FIG.
A chip 1 with a diameter of 0 μm is obtained.

In this way, the contact between the H-chip 1 and the p-carved pole 9 is made of GaAs or At with a mixed crystal ratio Z of 111! .

is close to zero, so the contact resistance Rc
is approximately the same as that of conventional UaAzAs.

B) In one chip, the contact resistance Rc accounts for about 60% of the series resistance R8. As a result, the series resistance R5 is reduced to approximately 5 Ω from the conventional approximately 10 Ω, thereby reducing heat generation at the contact portion and further extending the life of the element.

Moreover, as shown in FIG. 4, the H chip 1 is as shown in FIG.
Even if it is fixed on the conductive layer 8 of the submount 12 via the solder 11, and is connected via the p-type electrode 9, the central part of the connection surface should be flat without having a depression as in the conventional case. Therefore, the wettability of the solder 11 does not deteriorate, and the solder 11 adheres closely without forming a cavity. For this reason,
The thermal resistance does not exceed the design value, and the screening yield also improves.

It should be noted that the invention is not limited to the above-mentioned embodiments, and can be applied to the manufacture of BH hand conductor laser elements having other structures. For example, both of these are well known, such as a structure in which a light guide layer is provided next to the active layer to improve optical output, and a structure in which the buried layer is a two-layer structure and the lower layer is a blocking layer to reduce leakage current. The present invention can be applied to the manufacture of a BHH conductor laser device having a step between the double heterojunction structure and the buried layer.

[Brief explanation of the drawing]

11y, i is a world-f plane view showing a conventional HH nonconductor laser element.
Figure 1-Cross-section ■ shows a good fixing state, Figures 3 (a) to (e) are a fruit of non-invention 7#1iylJ
13 I semicircular body by PC - method for manufacturing a thermal element 1
The M group diagram and Figure 4 are the same (131-1 half-four body laser eight-inch cross-sectional view) showing the steady state. Ja
As substrate, 3...double heterojunction structure, 4. re-incorporated layer, 5...n-shaped rad layer, 6... active layer, 7.
・P bending rad layer, 8... Absent film, 9, 10...' 1 step, 11... Solder, 12... Submount,
13... Toto-do, 14... Semiconductor thin plate (wafer),
15... Growth & promotion layer, 16... Mesa etching groove,
17... Flattening claw 1.18... Conductive layer. Agent: Mr. Takashi Akira ゛・、・）

Claims (1)

[Claims] 1. A step of sequentially growing epitaxial layers on the main surface of the GaAs substrate to form a double heterojunction structure, a step of leaving the double heterojunction structure in a stripe shape by etching, and filling the portion removed by the etching. In the method for manufacturing a buried hetero-type semiconductor laser device comprising the step of forming a layer, Ga having a relatively low mixed crystal ratio is added to the uppermost layer when forming the double hetero junction structure.
A growth promoting layer made of AzAs is formed, and when the buried layer is formed, when the growth end of the buried layer reaches the growth promoting layer, epitaxial growth is continuously performed over the buried layer and the growth promoting layer to form GaAs or GaA.
1. A method for manufacturing a buried hetero semiconductor laser device, comprising forming a flattening layer that is not IA s and has a flat central surface.