JPH08111565A - Semiconductor optical element and manufacture thereof - Google Patents

Abstract

PURPOSE: To provide a method of easily manufacturing a semiconductor optical element excellent in element characteristics and having a mesa stripe region which is so structured as to prevent a leakage current from occurring. CONSTITUTION: An active layer 2, a clad layer 3, and a contact layer 4 are successively laminated on a semiconductor substrate 1, which is subjected to etched through an insulator mask for the formation of a mesa stripe region. The mask is removed, and current blocking layers 6 formed of semi-insulating high-resistance semiconductor are provided at least higher than the contact layer 4 on both the sides of the mesa stripe region so as to sandwich it in between them. The mesa stripe region and its vicinity are etched through an exposed semiconductor mask so as to remove the current blocking layer 6 deposited on the contact layer 4 to form a groove-shaped structure where the contact layer 4 serves as a bottom and the current blocking layers 6 serve as two sloping side faces. The current blocking layers 6 as the side faces of the above groove-shaped structure are covered with an insulator 8, and an electrode 10 is formed on the contact layer 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high resistance layer embedded semiconductor optical device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in order to improve the quality and functionality of semiconductor optical devices, there has been developed a technique for burying and growing a mesa stripe including an active layer having a width of about 1 to 2 μm in a high resistance layer to manufacture a semiconductor device. Has become important. The technique of burying and growing a high resistance layer on the mesa stripe without attaching an insulator mask to fabricate a device is indispensable for fabricating a complicated device such as an optical / electronic integrated circuit (OEIC). The reason is that the adhesion of the semiconductor polycrystal on the insulator mask and the abnormal growth of the semiconductor crystal due to the presence of the insulator mask make it difficult to manufacture a complicated device. In particular, in addition to lowering the embedded growth temperature of the semiconductor high resistance layer, which is promising for improving the characteristics of semiconductor optical devices, both adhesion of polycrystals on the insulator mask and abnormal growth are problems, and the mesa stripe A device manufacturing technique that does not require the above-mentioned insulator mask is important.

Japanese Unexamined Patent Publication No. 5-121722 discloses a conventional "semiconductor light emitting device and its manufacturing method". Hereinafter, a method of manufacturing the semiconductor light emitting device according to the above publication will be described with reference to FIGS. 1A to 1G are schematic cross-sectional views showing respective steps according to the manufacturing method, and FIG. 2 has a conventional mesa stripe region manufactured through the respective steps of FIG. It is a schematic sectional drawing which shows a semiconductor light-emitting device.

First, as shown in FIG. 1A, an active layer 2, a second conductivity type cladding layer 3 and a second conductivity type contact are formed on a semiconductor substrate 1 having a first conductivity. Layers 4 are laminated in sequence. Next, as shown in (b), an insulator mask 5 having a predetermined shape is formed at a predetermined position on the contact layer 4, which is the surface of the laminated body, and the mask 5 is used to perform etching (c ) Mesa stripe M
To form. Next, as shown in (d), after removing the insulator mask 5 on the mesa stripe M, the mesa stripe region M is sandwiched so as to cover the mesa stripe region M as shown in (e). The current blocking layer 6 made of a semi-insulating high resistance semiconductor is formed so that the heights on both sides are substantially equal to the height of the contact layer 4. Next, as shown in (f), a semiconductor mask 7 is provided at a predetermined position on the current blocking layer 6 so that at least the mesa stripe region M and its peripheral portion are exposed, and then the opening of the mask 7 is formed. Etching is performed on the current blocking layer 6 in the mesa stripe region M and its peripheral portion as shown in FIG.
It was removed in a letter shape. After that, a mask (not shown) is provided on the contact layer 4, an insulating layer 8 is provided, and then a polyimide layer is embedded in the V-shaped groove to form a dielectric layer 9. Then, the mask is removed and then the contact layer 4 is removed. The electrode 10 is formed to obtain the semiconductor light emitting device having the mesa stripe region M shown in FIG.

However, in such a conventional forming method, the current blocking layers 6 on both sides of the mesa stripe region M are scooped into a V shape, and the current blocking layer 6 is partially thinned. There was a problem. That is, in the structure of the current blocking layer 6 having such a V-shaped groove, the current blocking layers 6 on both sides of the mesa stripe are narrowed, and the distance between the bottom of the V-shaped groove and the semiconductor substrate 1 is narrowed, so that the leakage is prevented. Since the current increases and the device capacitance increases, the number of steps of filling a dielectric such as polyimide in the V-shaped groove increases,
It has been difficult to easily manufacture a semiconductor device having good device characteristics.

[0006]

SUMMARY OF THE INVENTION A first object of the present invention is to provide a semiconductor optical device having a mesa stripe region having a structure for preventing generation of leakage current in order to solve the above problems. .

A second object of the present invention is to provide a method of manufacturing a semiconductor optical device which can easily manufacture a semiconductor device having good device characteristics without the step of burying a dielectric such as polyimide.

[0008]

In order to achieve the first object, the invention according to claim 1 is a semiconductor optical device, which is provided on a semiconductor substrate having a first conductivity. A mesa stripe region including an active layer, a second conductive clad layer provided on the active layer, and a second conductive contact layer provided on the clad layer, and the mesa stripe And a current blocking layer made of a semi-insulating high resistance semiconductor, which is provided on both sides of the region and has a layer thickness that exceeds at least the height of the contact layer in the mesa stripe region.

Here, the invention of claim 2 is the same as claim 1.
In the semiconductor optical device described above, the current blocking layer may be provided only in a limited region on both sides of the mesa stripe region.

According to a third aspect of the present invention, in the semiconductor optical device according to the first aspect, the semiconductor optical device further includes a groove structure provided on both sides of the mesa stripe region, and the current blocking layer fills the groove structure. Further, the layer thickness may be at least larger than the height of the contact layer of the mesa stripe.

In order to achieve the above second object,
The invention according to claim 4 is a method for manufacturing a semiconductor optical device, wherein an active layer is laminated on a semiconductor substrate having a first conductivity, and a clad layer having a second conductivity is formed on the active layer. Stacking and sequentially stacking a second conductive contact layer on the clad layer, providing a first mask having a predetermined shape on the stacked portion, and interposing the first mask Forming a mesa stripe region by performing etching by etching, and having a layer thickness so as to cover the mesa stripe region and the height of both sides sandwiching the mesa stripe region is at least higher than the height of the contact layer. Forming a current blocking layer made of a semi-insulating high-resistance semiconductor, providing a second mask having a shape exposing the mesa stripe region and its peripheral portion, and through an opening of the second mask A contact layer of the mesa stripe region and the bottom surface by performing etching, characterized in that it comprises a step of forming a grooves construction and the side surface of the current blocking layer.

Here, the invention according to claim 5 is the invention according to claim 4.
In the method for manufacturing a semiconductor optical device described above, after the step of forming the mesa stripe region, an insulator is applied to a region that is separated from the other mesa stripes on both sides of the mesa stripe region by a predetermined distance. The steps may be performed.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor optical device according to the fourth aspect, in the mesa stripe region forming step, a groove structure is formed on both sides of the mesa stripe region. May be a step of forming the mesa stripe region.

[0014]

In the semiconductor optical device of the present invention, by forming the current blocking regions on both sides of the mesa stripe wider than before, it is possible to prevent the generation of leakage current and improve the device characteristics. is there.

Further, in the method for manufacturing a semiconductor optical device of the present invention, a semi-insulating high-resistance semiconductor is buried and grown on the mesa stripe without an insulator mask, and an extra semi-insulation formed on the mesa stripe is formed. Since a current blocking layer made of a semi-insulating high resistance semiconductor was formed on both sides of the mesa stripe by removing the conductive high resistance semiconductor by etching, the conventional step of embedding a dielectric material such as polyimide was performed. Therefore, a semiconductor optical device having good device characteristics can be easily manufactured.

Further, in the method for manufacturing a semiconductor optical device according to the present invention, when a semi-insulating high resistance semiconductor is buried and grown on the mesa stripe without an insulator mask, at least both sides of the mesa stripe region are contacted. A semi-insulating high-resistance semiconductor having a layer thickness that exceeds the layer height is formed, and etching is performed to form a groove structure with the contact layer as the bottom surface and the current blocking layer as the side surface. The area can be widened, and the characteristics of the obtained semiconductor optical device can be improved.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings.

When the constituent elements of the semiconductor optical device according to the present invention are the same as the constituent elements of the conventional semiconductor optical device shown in FIGS. 1 and 2, the same reference numerals as those constituent elements are used. The description of that part is omitted.

First, as shown in FIG. 3A, an active layer 2, a cladding layer 3 and a contact layer 4 are sequentially laminated on a semiconductor substrate 1, and as shown in FIG. A body mask 5 is provided, and etching is performed through this mask 5 to form a mesa stripe region M as shown in FIG. Next, after removing the insulator mask 5 on the mesa stripe region M as shown in FIG.
As shown in (e), a current blocking layer 6 made of a semi-insulating high-resistance semiconductor is formed on both sides of the mesa stripe region M so as to have a layer thickness at least larger than the height of the contact layer 4.

Next, as shown in (f), the current blocking layer 6
After the semiconductor mask 7 having a shape exposing the mesa stripe region M and its peripheral portion is provided thereon, the current of the semi-insulating high resistor on the contact layer 4 is passed through the opening of the semiconductor mask 7 as shown in FIG. By etching the blocking layer 6, a groove structure having the contact layer 4 as the bottom surface and the current blocking layer of the semi-insulating semiconductor as the side surface is formed. In this etching, the contact layer 4 made of a material different from that of the high resistance layer 6 is used as an etching stop layer. To make the cross-sectional shape after etching a groove structure,
A semi-insulating high resistance layer 6 having a layer thickness exceeding at least the height of the contact layer 4 is formed on both sides of the mesa stripe region M, and a mask pattern having a semiconductor mask opening width corresponding to the high resistance layer thickness is formed into a mesa. It is necessary to perform etching after forming it on the stripe region M. After that, by covering the current blocking layer 6 which is the side surface of the groove structure with the insulator 8 and forming the electrode 10 on the contact layer 4, a desired semiconductor optical device can be manufactured as shown in FIG. it can.

Here, after forming the mesa stripe region M, the regions without the mesa stripe on both sides of the mesa stripe region M are covered with an insulator, and the region is formed with a current of a semi-insulating high resistance semiconductor. When the blocking layer 6 is formed, the current blocking layer 6 having a layer thickness exceeding the height of the contact layer 4 can be formed in a shorter time than when the insulating coating is not performed. The reason is that the semiconductor raw material supplied on the insulator film diffuses into the exposed portions of the mesa stripe region M and the peripheral portions on both sides of the mesa stripe region M to increase the deposition rate. 5A to 5C are process diagrams for explaining the above-described method. In FIG. 5A, the mesa stripe region M and the peripheral portions on both sides thereof are opened on the semiconductor substrate 1. 3B is a cross-sectional view showing a state in which an insulator mask 5 is provided, and FIG. 6B is a cross-sectional view showing a state in which a current blocking layer 6 made of a semi-insulating high-resistance semiconductor covering the mesa stripe region M is formed. (C) is a cross-sectional view showing a state in which an insulator 8 is formed on the current blocking layer 6 and an electrode 10 is formed on the contact layer 4.

Further, as shown in FIG. 6A, the contact is formed by forming a groove structure on both sides of the mesa stripe region M before depositing the current blocking layer 6 of the semi-insulating high resistance material. The current blocking layer 6 having a layer thickness exceeding the height of the layer 4 can be formed in a shorter time than in the case where no groove structure is provided on both sides of the mesa stripe region M.
The reason is that when the current blocking layer 6 which is a high resistance layer is deposited, it is on both sides of the mesa stripe region M, and the region separated from the mesa stripe region M by the groove structure is one of the buried layers on both sides of the mesa stripe region M. This is because the embedded high resistance layer thickness that must be deposited is reduced. 6A to 6C are process diagrams for explaining the above-described method, and FIG. 6A shows regions on both sides of the mesa stripe region M on the semiconductor substrate 1 having a groove structure. 3B is a cross-sectional view showing a state in which the current blocking layer 6 made of a semi-insulating high-resistance semiconductor that covers the mesa stripe region M and fills the groove structure is formed, FIG. 6C is a cross-sectional view showing a state in which the insulator 8 is formed on the current blocking layer 6 and the electrode 10 is formed on the contact layer 4.

Next, a concrete example will be described.

Example 1 An active layer of an InGaAsP semiconductor crystal corresponding to an emission wavelength of 1.3 μm, a p-type InP clad layer, and a p-type InGaAsP contact layer were sequentially grown on an n-type InP substrate, and the crystal surface was grown. After the insulator stripe mask pattern is formed, dry etching is performed.

[0025]

[Outside 1]

Was formed. Next, the insulator mask on the mesa stripe was removed. Thereafter, an Fe-doped semi-insulating InP high resistance layer was grown, and then an InGaAs crystal used as an opening mask for etching the high resistance layer was grown.
InGa so as to open the high resistance layer on the mesa stripe
An As mask pattern was formed, and a groove structure having an InGaAsP contact layer as the bottom surface and a semi-insulating InP high resistance current blocking layer as the side surface was formed by wet etching using hydrochloric acid. After that, only the current blocking layer, which is the side surface of the groove structure, was covered with a SiO ₂ insulator, an electrode was formed on the InGaAsP contact layer, and a semiconductor laser was manufactured. As a result, the characteristic of this semiconductor laser is that the element capacitance is 1/2 as compared with the semiconductor laser manufactured by providing the high resistance current blocking layer having V-shaped grooves on both sides of the mesa stripe using the conventional technique. The transmission threshold was reduced to 2/3 or less, and the maximum output was increased to 1.5 times or more.

Example 2 InGaAs / InGaAs having an emission wavelength of 1.55 μm was formed on an n-type InP substrate.
P strained multiple quantum well active layer, P type InP clad layer, p
Type InGaAsP contact layers are grown in sequence, an insulator stripe mask pattern is formed on the crystal surface, and then wet etching is performed.

[0028]

[Outside 2]

Was formed. Next, the insulator mask on the mesa stripe was removed. Thereafter, a Fe-doped semi-insulating InP high resistance layer was grown, and then an InGaAs crystal used as an opening mask for etching the high resistance layer was grown. InGaAs so as to open the high resistance layer on the mesa stripe
A mask pattern was formed, and a groove structure having a InGaAsP contact layer as the bottom surface and a semi-insulating InP high resistance current blocking layer as the side surface was formed by hydrochloric acid wet etching. After this, only the current blocking layer on the side surface of the groove structure is S
A semiconductor laser was manufactured by covering with an iO ₂ insulator and forming electrodes on the InGaAsP contact layer. As a result, the characteristic of this semiconductor laser is 1 compared with the semiconductor laser manufactured by providing the high resistance current blocking layer having V-shaped grooves on both sides of the mesa stripe using the conventional technique.
/ 2 or less, the oscillation threshold decreased to 2/3 or less, and the maximum output increased to 1.5 times or more.

(Example 3) On an n-type InP substrate, an active layer of an InAsP / InGaAsP strained multiple quantum well corresponding to an emission wavelength of 1.3 μm, a p-type InP clad layer, and a p-type I.
nGaAsP contact layers are grown in sequence, an insulator stripe mask pattern is formed on the crystal surface, and then dry etching is performed.

[0031]

[Outside 3]

Was formed. Then, after removing the insulator mask on the mesa stripe, the regions without mesa stripe on both sides of the mesa stripe region are covered with SiO ₂ insulator,
A Fe-doped semi-insulating InP high resistance layer was grown.
As a result, the time for forming the semi-insulating InP high resistance layer is
It could be shortened to 1/10 as compared with the case where the SiO ₂ insulator is not coated on both sides of the mesa stripe region. Next, an InGaAs crystal using the high resistance layer as an opening mask for etching was grown. I to open the high resistance layer on the mesa stripe
An nGaAs mask pattern was formed, and a groove structure having an InGaAsP contact layer as the bottom surface and a semi-insulating InP high resistance current blocking layer as the side surface was formed by wet etching using hydrochloric acid. After that, only the current blocking layer, which is the side surface of the groove structure, was covered with a SiO ₂ insulator, an electrode was formed on the InGaAsP contact layer, and a semiconductor laser was manufactured. As a result, the characteristic of this semiconductor laser is that the element capacitance is 1/2 as compared with the semiconductor laser manufactured by providing the high resistance current blocking layer having V-shaped grooves on both sides of the mesa stripe using the conventional technique. Below, the oscillation threshold was reduced to 2/3 or less, and the maximum output was increased to 1.5 times or more.

Example 4 On an n-type InP substrate, an active layer of a InAsP / InGaAsP strained multiple quantum well corresponding to an emission wavelength of 1.3 μm, a p-type InP clad layer, and a p-type I.
nGaAsP contact layers are grown in sequence, an insulator stripe mask pattern is formed on the crystal surface, and then dry etching is performed.

[0034]

[Outside 4]

Grooves were formed on both sides of the mesa stripe.
Then after removing the insulator mask on the mesa stripes,
A Fe-doped semi-insulating InP high resistance layer was grown.
As a result, the time for forming the semi-insulating InP high resistance layer is
1 more than if there is no groove structure on both sides of the mesa stripe area
It was possible to shorten to / 5. Next, an InGaAs crystal used as an opening mask for etching the high resistance layer was grown. An InGaAs mask pattern is formed so as to open the high resistance layer on the mesa stripe, and wet etching with hydrochloric acid is used to form I.
Semi-insulating InP with nGaAsP contact layer as bottom
A groove structure having a high resistance current blocking layer as a side surface was formed. After that, only the current blocking layer, which is the side surface of the groove structure, was covered with a SiO ₂ insulator, an electrode was formed on the InGaAsP contact layer, and a semiconductor laser was manufactured. As a result, the characteristic of this semiconductor laser is that the element capacitance is 1/2 as compared with the semiconductor laser manufactured by providing the high resistance current blocking layer having V-shaped grooves on both sides of the mesa stripe using the conventional technique. Below, the oscillation threshold was reduced to 2/3 or less, and the maximum output was increased to 1.5 times or more.

In each of the above embodiments, InGaAsP
The present invention has been applied to a semiconductor element of a semiconductor material of
It is needless to say that the present invention is not limited to these and other semiconductor materials and other semiconductor optical devices have the same excellent effects.

[0037]

As described above, according to the present invention,
When a semi-insulating high resistance semiconductor is embedded and grown on the mesa stripe without an insulator mask to make a semiconductor device, a semi-insulating high resistance semiconductor is embedded and grown on the mesa stripe by an insulator mask. Good semiconductor element characteristics equivalent to those of the above semiconductor element can be realized.

Therefore, the method for manufacturing a semiconductor optical device according to the present invention is extremely useful for manufacturing a semiconductor optical device which requires complicated process steps such as an optical / electrical integrated circuit (OEIC).

[Brief description of drawings]

FIG. 1 is a vertical sectional view of each step for explaining a conventional method for manufacturing a semiconductor optical device.

FIG. 2 is a vertical cross-sectional view showing the configuration of a conventional semiconductor optical device manufactured according to the manufacturing method shown in FIG.

FIG. 3 is a vertical cross-sectional view of each step for explaining one embodiment of the method for manufacturing a semiconductor optical device of the present invention.

FIG. 4 is a vertical cross-sectional view showing the structure of a semiconductor optical device of the present invention manufactured according to the manufacturing method shown in FIG.

FIG. 5 is a vertical cross-sectional view of each step for explaining another embodiment of the method for manufacturing a semiconductor optical device of the present invention.

FIG. 6 is a vertical sectional view of each step for explaining still another embodiment of the method for manufacturing a semiconductor optical device of the present invention.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Active Layer 3 Cladding Layer 4 Contact Layer 5 Insulator Mask 6 Current Blocking Layer 7 Semiconductor Mask 8 Insulating Layer 9 Dielectric Layer 10 Electrode M Mesa Stripe Region

Front page continuation (72) Inventor Yoshiaki Kadota 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (6)

[Claims] 1. An active layer provided on a semiconductor substrate having a first conductivity, a second conductive clad layer provided on the active layer, and an active layer provided on the clad layer. A mesa stripe region formed of a contact layer having a second conductivity, and a semi-layer having a layer thickness that is provided in regions on both sides of the mesa stripe region and that exceeds at least the height of the contact layer in the mesa stripe region. A semiconductor optical device comprising a current blocking layer made of an insulating high resistance semiconductor. 2. The semiconductor optical device according to claim 1, wherein
The semiconductor optical device, wherein the current blocking layer is provided only in a limited region on both sides of the mesa stripe region. 3. The semiconductor optical device according to claim 1,
The current blocking layer further includes a groove structure provided on both sides of the mesa stripe region, and the current blocking layer has a layer thickness at least higher than the height of the contact layer of the mesa stripe. A semiconductor optical device characterized by being present. 4. An active layer is laminated on a semiconductor substrate having a first conductivity, a clad layer having a second conductivity is laminated on the active layer, and a second conductivity is formed on the clad layer. Forming a mesa stripe region by sequentially laminating a contact layer having a layer, a step of providing a first mask having a predetermined shape on the laminated portion, and etching through the first mask. And a current blocking layer formed of a semi-insulating high-resistance semiconductor having a layer thickness so as to cover the mesa stripe region and the height of both sides sandwiching the mesa stripe region exceeds at least the height of the contact layer. And a step of providing a second mask having a shape in which the mesa stripe region and its peripheral portion are exposed, and etching through the opening of the second mask A contact layer of the stripe region and a bottom surface, a method of manufacturing a semiconductor optical device, which comprises a step of forming a grooves construction and the side surface of the current blocking layer. 5. The method for manufacturing a semiconductor optical device according to claim 4, wherein after the step of forming the mesa stripe region, a predetermined space is provided between the mesa stripe region and other mesa stripes on both sides of the mesa stripe region. A method for manufacturing a semiconductor optical device, which comprises performing a step of covering an insulating region with an insulator. 6. The method for manufacturing a semiconductor optical device according to claim 4, wherein in the mesa stripe region forming step, a mesa stripe region is formed by forming a groove structure on both sides of the mesa stripe region. And a method for manufacturing a semiconductor optical device.