JPS59208797A - Josephson element integrated circuit device - Google Patents
Josephson element integrated circuit deviceInfo
- Publication number
- JPS59208797A JPS59208797A JP58084308A JP8430883A JPS59208797A JP S59208797 A JPS59208797 A JP S59208797A JP 58084308 A JP58084308 A JP 58084308A JP 8430883 A JP8430883 A JP 8430883A JP S59208797 A JPS59208797 A JP S59208797A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- josephson
- josephson element
- integrated circuit
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明はジョセフソン素子集積回路装置に係り、特に
その集積度向上のためのジョセフソン素子の構成に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a Josephson element integrated circuit device, and particularly to a configuration of a Josephson element for improving the degree of integration thereof.
第1図は従来のジョセフソン素子の構造を示す断面図で
、+1+は基板、(2)は基板(l]の上に形成された
グランドプレーン、(3)は更にその上に形成された第
1の絶縁層、(4)は第1の絶縁層(3)の上の一部に
形成された下部導体、(5)は下部導体(4)の上の一
部に形成された絶縁薄膜、(6)は絶縁薄膜(6)の上
がら、第1の絶縁層(3)上の下部導体(4)の形成さ
れていない部分にわたって形成された上部導体、(7)
は絶縁薄膜(5)が形成されていない下部導体(4)の
部分の上から上部導体(6)の上にわたって形成された
第2の絶?7層、(8)は更にその上に形成された制御
線域たは配線である。Figure 1 is a cross-sectional view showing the structure of a conventional Josephson element, where +1+ is the substrate, (2) is the ground plane formed on the substrate (l), and (3) is the ground plane formed on the substrate (l). (4) is a lower conductor formed on a part of the first insulating layer (3); (5) is an insulating thin film formed on a part of the lower conductor (4); (6) is an upper conductor formed over the upper part of the insulating thin film (6) and the part where the lower conductor (4) is not formed on the first insulating layer (3); (7)
is a second insulation film formed from above the portion of the lower conductor (4) where the insulating thin film (5) is not formed to above the upper conductor (6). In the seventh layer, (8) is a control line area or wiring formed thereon.
そして、このジョセフソン赤子を用いた集積回路装置は
通常グランドプレーンの上に、図示のように絶縁薄膜(
5)を下部導体(4)と上部導体(5)とて私んで構成
されたジョセフソン接合を含んで種々のインダクタンス
、抵抗体などで構成されるもので、グランドプレーンは
不可欠である。An integrated circuit device using this Josephson baby usually has an insulating thin film (as shown in the figure) on top of the ground plane.
5) is composed of various inductances, resistors, etc., including a Josephson junction composed of a lower conductor (4) and an upper conductor (5), and a ground plane is essential.
ところで、従来のジョセフソン素子は上述のようにグラ
ンドプレーンの片側のみに構成されているので、集程1
回路化したとき、その集積度の向上に不利であった。By the way, since the conventional Josephson element is configured only on one side of the ground plane as mentioned above,
When circuitized, it was disadvantageous in improving the degree of integration.
この発明は以上のような点に娩みてなされたもので、グ
ランドプレーンの両側に別個のジョセフソン素子を構成
することによって集積度の高いジョセフソン素子集積回
路装貌′1を提供するものである0
〔発明の実施例〕
第2図はこの発明の一実施例におけるジョセフソン素子
の構成を示す断面図で、第1図の従来例と同一符号は同
等部分を示す。この実施例では、グランドプレーン(2
)の上側に第1図と同様な第1のジョセフソン素子を、
グランドプレーン(2iの下に第2のジョセフソン素子
を形成している。すなわち、基板[1)の上に下部導体
(14)が直接形成されるとともに、これに並べて制御
線(18)が形成されている。そして、この制御線Q8
jを覆うように第2の絶m!(171が形成され、下部
導体(14)の表面の一部に形成された絶縁薄膜QFi
)の上から第2の絶縁層(17)の上(こわたって上部
導体(16jが形成されている。上部導体(1G)の上
から下部導体(14)の上の絶縁薄膜(15)が形成さ
れていない部分にわたって第1の絶縁層(131が形成
され、その上にグランドプレーン(2)が形成されてい
る。そして、このグランドプレーン(2)の上には第1
図と全く同様のもう一つのジョセフソン素子が形成され
、グランドプレーン(2)の上側および下側にそれぞれ
第1および第2のジョセフソン素子が形成された形(こ
なっている。このようGこ形成されたジョセフソン接合
を用いてジョセフソン素子集積回路装置を構成すること
によって集積度を向上させることができる。The present invention has been made in view of the above points, and provides a Josephson element integrated circuit arrangement '1 with a high degree of integration by configuring separate Josephson elements on both sides of a ground plane. 0 [Embodiment of the Invention] FIG. 2 is a sectional view showing the configuration of a Josephson element in an embodiment of the present invention, and the same reference numerals as in the conventional example of FIG. 1 indicate equivalent parts. In this example, the ground plane (2
), a first Josephson element similar to that shown in Figure 1 is placed above the
A second Josephson element is formed under the ground plane (2i). That is, the lower conductor (14) is formed directly on the substrate [1], and the control line (18) is formed next to it. has been done. And this control line Q8
The second orgasm covers J! (171 is formed, and an insulating thin film QFi formed on a part of the surface of the lower conductor (14)
) The upper conductor (16j is formed over the second insulating layer (17). The insulating thin film (15) is formed over the lower conductor (14) from above the upper conductor (1G). A first insulating layer (131) is formed over the portion that is not covered, and a ground plane (2) is formed on it.
Another Josephson element exactly similar to the figure is formed, with first and second Josephson elements formed above and below the ground plane (2), respectively. By constructing a Josephson element integrated circuit device using the Josephson junction thus formed, the degree of integration can be improved.
以上説明したように、この発明ではグランドプレーンの
表裏両側にジョセフソン接合を形成し、これを用いてジ
ョセフソン素子集積回路装置を構成したので、従来と同
等の微細加工技術でも2倍の集積2をイGることができ
る。As explained above, in this invention, Josephson junctions are formed on both the front and back sides of the ground plane, and these are used to construct a Josephson element integrated circuit device. You can do it.
第」図は従来のジョセフソン素子集積回路装置に用いる
ジョセフソン素子の構造を示す断面V1第2図はこの発
明の一実施例に用いるジョセフソン素子の構造を示す断
面図である。
図において、(1)は基板、(2)はグランドプレーン
、(3)は絶縁層、(・1)は第2の下部導体、(5)
(コ第2の絶縁薄膜、(6)は第2の上部導体、(I3
)は絶縁層、(14)は第1の下部導体、(15)は第
4の絶縁薄膜、(1(<1は第廓の上部導体である。
なi・、図中同一符号は同一または相当部分を示す。
代理人 大岩増雄
第1図
第2図1 is a cross-sectional view showing the structure of a Josephson device used in a conventional Josephson device integrated circuit device. FIG. 2 is a cross-sectional view showing the structure of a Josephson device used in an embodiment of the present invention. In the figure, (1) is the substrate, (2) is the ground plane, (3) is the insulating layer, (・1) is the second lower conductor, (5)
(7) is the second insulating thin film, (6) is the second upper conductor, (I3
) is an insulating layer, (14) is a first lower conductor, (15) is a fourth insulating thin film, (1 (<1 is the upper conductor on the outer side. The corresponding part is shown. Agent Masuo Oiwa Figure 1 Figure 2
Claims (1)
されたジョセフソン接合を用いて構成したことを特徴と
するジョセフソン素子集積回路装置。 (2)基板の上に直接形成した第1の下部導体と、この
第1の下部導体の表面の一部に形成した第1の絶縁薄膜
を介して第1の上部導体とを対向させてなる第1のジョ
セフソン接合、並びに上記第1の下部導体および上記第
1の上部導体の上に絶縁層を介して形成したグランドプ
レンの上にこれと絶縁して形成した第2の下部導体と、
この第2の下部導体の表面の一部に形成した第2の絶縁
薄膜を介して第2の上部導体とを対向させてなる第2の
ジョセフソン接合を用いたことを特徴とする特許請求の
範囲第1項記載のジョセフソン素子集信回路装置な。[Claims] +1+ A Josephson element integrated circuit device characterized in that it is constructed using Josephson junctions formed on both the front and back surfaces of a ground plane. (2) A first lower conductor formed directly on the substrate and a first upper conductor facing each other via a first insulating thin film formed on a part of the surface of the first lower conductor. a first Josephson junction, and a second lower conductor formed on and insulated from a ground plane formed on the first lower conductor and the first upper conductor via an insulating layer;
A second Josephson junction is used in which the second lower conductor is opposed to the second upper conductor through a second insulating thin film formed on a part of the surface of the second lower conductor. A Josephson element integrated circuit device as described in Scope 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58084308A JPS59208797A (en) | 1983-05-12 | 1983-05-12 | Josephson element integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58084308A JPS59208797A (en) | 1983-05-12 | 1983-05-12 | Josephson element integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59208797A true JPS59208797A (en) | 1984-11-27 |
Family
ID=13826859
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58084308A Pending JPS59208797A (en) | 1983-05-12 | 1983-05-12 | Josephson element integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59208797A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62165378A (en) * | 1986-01-14 | 1987-07-21 | Nec Corp | Josephson junction device composed of laminated junctions with different current densities |
JPS62232982A (en) * | 1986-04-03 | 1987-10-13 | Nec Corp | Josephson junction device |
-
1983
- 1983-05-12 JP JP58084308A patent/JPS59208797A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62165378A (en) * | 1986-01-14 | 1987-07-21 | Nec Corp | Josephson junction device composed of laminated junctions with different current densities |
JPH053754B2 (en) * | 1986-01-14 | 1993-01-18 | Nippon Electric Co | |
JPS62232982A (en) * | 1986-04-03 | 1987-10-13 | Nec Corp | Josephson junction device |
JPH0546992B2 (en) * | 1986-04-03 | 1993-07-15 | Nippon Electric Co |
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