JPS59208622A - Interface circuit - Google Patents

Abstract

PURPOSE:To improve checking efficiency on an interface and to transmit/receive correct data by providing a means for sending formal data and its complement data to the sending side as parallel data and a control means for sending the data successively and checking these data on the receiving side. CONSTITUTION:A cut d-type FF1-1 on the sending side latches data signals ID1-ID4 by a signal SET and applies the outputs to a 4-input selector 1-2. The output of a d-type FF1-3 is turned to ''1'' by a signal ST, a binary counter 1-4 is actuated and the inputs of the selector 1-2 are sent to the interface as signals DATA1-DATA4. The signals DATA1-DATA4 are checked by a cut d-type FF3-1, a 4-input comparator 3-2, a d-type FF3-3, and an inverter 3-4 on the receiving side. Thus, the checking efficiency of the data on the interface is improved and correct data transmission/reception is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interface circuit for preventing erroneous transmission when transferring parallel data.

In the conventional ink circuit of this type, the sending side adds a parity pit to the formal data and sends it out, and the receiving side performs a parity check based on the formal data and the parity pit to check the normality of the data. It was a circuit to do this.

In parallel transfer interface circuits, if only the parity addition function and parity check function are used, data errors of 2 or more bits occur, and the receiving side produces incorrect data, resulting in a decrease in reliability and quality. It turns out.

An object of the present invention is to provide an interface circuit that increases the data error checking rate on the interface and transmits and receives only correct data.

In the interface circuit of the present invention, the sending side includes means for sending formal data and its complement data as parallel data;
The receiving side includes means for receiving the formal data and complement data, and a means for receiving the formal data and complement data, and compares the received formal data and the complement data to determine whether the data is in a complement relationship. and means for identifying whether the received data is formal data or complement data.

On the sending side, first formal data is sent onto the interface from a circuit that sends formal data and complement data, and then data obtained by taking the complement of the formal data is sent. The control circuit determines the transmission time and transmission interval of formal data and complement data, and selects whether the data to be transmitted on the interface is formal data or complement data. Note that the order of formal data and complement data may be either first. On the receiving side, a circuit that receives official data and complement data receives data from the interface at each reception timing, and a circuit that checks normality checks that the first data and second data are in a complementary relationship. It is checked if it is, and if it is, the data in the official data receiving circuit is treated as normal data.

FIG. 1 shows an embodiment of the sending side of the present invention. The input/output timing is shown in FIG. 1 to 4 from the data signal [A
] is input, and the clock input CK of the signal SET is input.
Cad de Taifu 7 Rip 7 at the input timing to
It is latched to 0 bits 1-1. Also, when the signal ST is input to the clock input CK, when the Q of the de-type flip-flops 1-3 becomes logic 1, the enable input ETIEP is input.
, when the human clear CLR becomes logic 1, the binary counter 1-4 operates, and the output Q0 becomes logic 1, the value [A] of the input signals IA to 4A of the selector 1-2 becomes the signal DATA1 to 4 on the interface. sent to.

Next, the counter advances and outputs Q. When QD and QD become logic 1, the complement (A) of the value [A] of the input signals IB to 4B of the four-man power selector 1-2 is sent to the signals DATA1 to DATA4. Also, when the values (A) and [A] are sent out, the strobe signal STR is at the 11 center of the data. Logic 0 to counter output. Q.B.

It is sent at the timing when Qo becomes logic 1.

FIG. 3 shows an embodiment of the receiving side of the present invention. Further, the input/output timing is shown in FIG. Signal D on the interface
The first data input from ATA1 to ATA4 is latched into the quad-te type flip-flop 3-1 at the timing when the strobe signal STR is input to the clock input CK.

The values of the output signals IQ to 4Q of the quad type flip-flop 3-1 and the complement inverted by the second input data signal inverter 3-4 are input to the four-man comparator 3.
-2, and if the former signal input BO~3 and the latter signal input AO~3 are equal, the second strobe signal S
At the timing of TR, a signal OK indicating that the data appearing on signals OD1 to OD4 is normal is output.

In addition to transferring parallel data, by sending normal data and complement data twice, errors of 2 or more bits that cannot be detected by parity checks can be detected without fail, greatly improving reliability between interfaces.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the sending G11l of the embodiment of the present invention, FIG. 2 is a timing diagram showing its operation, and FIG. 3 is a block diagram showing the receiving side of the embodiment of the present invention. FIG. 4 is a timing diagram showing the operation. 1-1... Quad fist type flip-flop, 1-2... Four-man selector, 1-3...
...De type contest flip flop, 1-4...
... Binary counter, 3-1 ... Quad.
De type flip-flop, 3-2...4
Human comparator, 3-3...de type flip-flop, 3-4...inverter. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] The transmitting side has means for transmitting formal data and complement data as parallel data, and control means for sequentially transmitting the formal data and complement data f, and the receiving side has means for receiving formal data and complement data. and means for comparing the received formal data and complement data to check that both data are in a complement relationship, and means for identifying whether the received data is formal data or complement data? interface circuit with.