JPH02312418A - Communication equipment for vehicle use - Google Patents

Abstract

PURPOSE:To transmit more information by the limited number of bits by inverting a logical value of parity information in accordance with flag information related to communication. CONSTITUTION:Parity information for detecting a communication error is added to data information and transmitted. Also, this equipment is provided with an inverting means 4 for inverting a logical value of the parity information in accordance with flag information related to communication. For instance, at a usual time, when the flag information for showing abnormality of a system is obtained in a state that a transmission means 2 adds the parity information of an even number parity and transmits it, the logical value of the parity information is inverted by the inverting means 4, therefore, the parity information of an odd number parity is added to the data information. In such a way, a discriminating means 6 can discriminate the flag information and a communication error, based on the logical value of the parity information added to the data information. Accordingly, various information related to the data and the communication can be transmitted by the limited number of bits.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a vehicle communication device, and more particularly, to a vehicle communication device that can also transmit information regarding communication errors and flag information regarding communication. .

(Prior art) In recent years, the use of electronics in vehicles has been promoted, and information regarding the operation of multiple operation parts is transmitted using fewer signal lines, and the corresponding actuators are operated by control of the CPU. I have to.

As a conventional vehicle communication device for transmitting such information, the one shown in FIG. 5 is known.

The CPU 101 is connected to a parallel/serial converter H 107 via a data bus 103 and a signal line 105, and parallel data consisting of a plurality of bits is transmitted via the data bus 103, and parity information for error detection, i.e. Parity bit information dedicated to error detection is transmitted via signal line 105. The parallel/serial converter 107 converts the input parallel data into serial data, adds the parity bit information to the serial data, and outputs the serial data. The PWM transmitter 109 pulse width modulates the input serial data information and transmits it. This transmission information is demodulated by a PWM receiver 111 and then converted into parallel data information by a serial/parallel converter 113. Among the parallel data information, multiple bits of parallel data are transmitted via the data bus 115, and parity dot information is transmitted via the signal line 117. The CPU 119 receives multiple bits of parallel data as well as parity bit information, performs a parity check in consideration of the parity bit information, and determines whether a communication error has occurred.

(Problem to be Solved by the Invention) However, the conventional example shown in FIG. A problem has arisen in that when the number of pieces of information in the data increases, it is not possible to secure enough bits to transmit other information.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a communication device for a vehicle that can transmit various information regarding data and communication using a limited number of bits.

[Structure 1 of the Invention (Means for Solving the Problems) A vehicle communication device provided by the present invention to achieve the above-mentioned object, as shown in FIG. a transmission means 2 for transmitting the parity information by adding it to the information; an inversion means 4 for inverting the logical value of the parity information according to flag information related to communication; The apparatus includes a determination means 6 for determining flag information and communication errors based on the logical value of parity information added to data information.

(Operation) The present invention adds parity information for detecting communication errors to data information and transmits the data. It also includes inverting means 4 for inverting the logical value of the parity information in accordance with flag information regarding communication.

For example, when flag information indicating a system abnormality is obtained while the transmission means 2 is transmitting data information with even parity added to the parity information in normal times, the logical value of the parity information is inverted by the inversion means 4. Therefore, parity information of odd parity is added to the data information. This allows the determining means 6 to determine flag information and communication errors based on the logical value of the parity information added to the data information.

(Embodiment) An embodiment of the present invention will be described in detail below with reference to the drawings.

First, the configuration will be explained with reference to FIG.

CPtJl is connected to a parallel/serial converter 7 via a data bus 3 and a signal line 5.

Data information of parallel data consisting of a plurality of bit data is transmitted via the data bus 3, and the signal line 5
Parity bit information, that is, parity information for error detection, is transmitted via the . The parallel/serial converter 7 is connected to the PWM transmitter 9, converts the input parallel data into serial data, adds the parity information to the serial data, and outputs the serial data to the PWM transmitter 9.

To explain the parity information here, for example, when error detection using even parity is set in normal times, the number of H-level bit data is detected among the data information consisting of multiple bit data, and this H-level data is detected. If the number of level bit data is odd, the logic value of the parity information is set to H level. Conversely, if the number of bit data of one level is an even number, the logical value of the parity information is set to L level. Furthermore, as soon as flag information indicating that the system is unsteady is obtained, CPjJl inverts the logic value of the parity information, so the parallel/serial converter 7
In this case, parity information similar to that used in error detection using odd parity is added to data information.

The PWM transmitter 9 has a pulse width modulation circuit and a transmission circuit, and pulse width modulates the data information of the input serial data and the parity 6 information added to this data information and sends it to the PWM receiver 11. .

The PWM receiver 11 has a receiving circuit and a demodulating circuit, and upon receiving the transmitted information from the PWM transmitter 9, that is, the data information and the parity information added to this data information, demodulates it into the original signal. The PWM receiver 11 is connected to a serial/parallel converter 13 and outputs the demodulated signal, that is, received information to the serial/parallel converter 13.

The serial/parallel converter 13 converts input serial reception information into parallel information. Further, the serial/parallel converter 13 is connected to the CPU 19 via a data bus 15 and a signal line 17, and among the converted parallel information, data information of parallel data consisting of a plurality of pieces of data is transferred to the data path controller 5. At the same time, parity information added to this data information is transmitted via the signal line 17.

When the CPU 19 receives data information and parity information, it executes a parity check on these information to determine whether a communication error has occurred. For example, if the number of l'' level bit data among a plurality of bit data of data information and parity information is an even number, it is determined that communication has been properly performed. In addition, if the logical value of the parity information is inverted, that is, if the number of Trubel bit data is an odd number among all the data information and parity information, the system may be unsteady or a communication error may occur. judge what has happened.

Next, the operation will be explained with reference to FIGS. 3 and 4.

First, the operation of the system during normal operation will be explained.

Original data as shown in FIG. 3(A) is output from the CPU 1. That is, Trubel's bit data b1. level bit data b 2. Trubel bit data b3. L level bit data b4°b 5. b6.
The bit data b8 of Trubel is transmitted via the data bus 3, and the bit data b6 and the bit data b
At the timing between 8 and 8, Trubel's flag data F
e is transmitted via signal line 5.

In step 21 shown in FIG. 4, it is determined whether the system is normal or unsteady based on the value of the abnormality flag bit of the system, that is, the flag data Fe. If the value of the flag data Fe is Torbel in step 21, it is determined that the system is normal, and the process proceeds to step 23.

In step 23, the number of Trubel bit data among the bit data other than the flag data Fe is counted.

Next, in step 25, it is determined whether the number of bit data of the Trubel is an even number or not. If it is an odd number, the process proceeds to step 27 and the bits of parity information, that is, the parity bit, are determined as shown in FIG. 3(B). Set the logical value of bw to trubel. Also, if the number of Trubel bit data is an even number in step 25, step 2
Proceed to step 9 and set the logical value of the parity bit bw to trubel.

The data information consisting of these multiple pieces of data and the parity information added to this data information are CPLJ19
, the CPU 19 determines whether a communication error has occurred based on the logical value of the parity information. That is, the CPU 19 executes a parity check between data information and parity information, and determines that communication has been properly performed if the number of Trubel bit data among these pieces of information is an even number.

Next, the effect when the system is unsteady will be explained.

When the system is unsteady, CPU1
), outputs the Trubel flag data Fe.

In step 21 shown in FIG. 4, it is determined that the system is unsteady based on the flag information Fe at the 1'' level, and the process proceeds to step 33.

In step 33, the number of bit data other than the flag data Fe, and the number of bits 1 to 1 of the trubel, is counted. Next, in step 35, it is determined whether the number of bit data of the Trubel is an even number or not. If it is an odd number, the process proceeds to step 37 and the parity bit bw shown in FIG. 3(D) is determined.
The logical value of is set to L level. . Conversely, step 3
If the number of H level bit data is an even number in step 5, the process advances to step 39 and the logic value of the parity bit bw is set to the H level.

When the data information consisting of these plurality of bit data and the parity information added to this data information are input to the CPU 19, the CPU 19 determines flag information or a communication error based on the logical value of the parity information. That is, C
The PU 19 executes a parity check between the data information and the parity information, and determines that a communication error has occurred or that the system is not normal if the number of H level bit data is an odd number.

As described above, since the logic value of the parity bit is inverted when the system is not normal, this single parity bit can contain flag information and information regarding communication errors.

In the above-described embodiment, the case where error detection using even parity is set is explained as an example, but the present invention can also be applied to a case where error detection using odd parity is set.

[Effects of the Invention] As explained above, according to the present invention, since the logical value of parity information is inverted according to communication-related flag information, more information can be transmitted using a limited number of bits. can do.

[Brief explanation of the drawing]

FIG. 1 is a claim correspondence diagram, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a signal waveform diagram showing transmitted data information and parity information, and FIG. FIG. 5 is a flow chart showing the operation of the embodiment shown in the figure, and FIG. 5 is a block diagram showing a conventional example. 2...Transmission means 4...Inversion means 6...Discrimination means

Claims (1)

[Scope of Claims] Transmission means for adding parity information to data information and transmitting the data information for detecting communication errors; inversion means for inverting the logical value of the parity information according to flag information regarding communication; A communication device for a vehicle, comprising: determination means for determining flag information and a communication error based on the logical value of parity information added to the data information when the data information transmitted from the means is received. .