JPS59204305A - Insulation type current amplifier - Google Patents

Insulation type current amplifier

Info

Publication number
JPS59204305A
JPS59204305A JP58078667A JP7866783A JPS59204305A JP S59204305 A JPS59204305 A JP S59204305A JP 58078667 A JP58078667 A JP 58078667A JP 7866783 A JP7866783 A JP 7866783A JP S59204305 A JPS59204305 A JP S59204305A
Authority
JP
Japan
Prior art keywords
signal
current
differential amplifier
amplifier
waveform
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58078667A
Other languages
Japanese (ja)
Inventor
Akira Ozawa
明 小澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Co Ltd
Original Assignee
Shinko Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Co Ltd filed Critical Shinko Electric Co Ltd
Priority to JP58078667A priority Critical patent/JPS59204305A/en
Publication of JPS59204305A publication Critical patent/JPS59204305A/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE:To obtain an insulation type current amplifier which outputs a large output and is manufactured in simple constitution by providing a differential amplifier, current control element, switching means, and feedback control. CONSTITUTION:A signal S1 when outputted by a D/A converter 4 is voltage- amplified by the differential amplifier 13 and current-amplified by the current control element 14 to obtain a signal S2. Therefore, the waveform of the signal S2 is equal to that of the signal S1. The S2 flows through the center tap of the primary winding of a transistors (TR) 15 and 16, and feedback means in order when a TR16 is on or through the center tap of the primary winding, a TR17, and the feedback means 18 in order when the TR17 is on. When currents flowing in the collectors of the TRs 16 and 17 are signals S3 and S4, the S3 and S4 are signals which alternate a section of the same waveform with the S2 and a section of level 0. Consequently, the waveform obtained by the full-wave rectification 25 of the secondary-side output of the TR15, i.e. the waveform of the voltage across a load resistance Rl is the same with the signal S1.

Description

【発明の詳細な説明】 この発明はアナログ信号を絶縁増幅する絶縁形電流増幅
器に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an isolated current amplifier that isolates and amplifies analog signals.

マイクロコンピュータ等の電子回路で演算した結果をア
ナログ信号に変換し、このアナログ信号によって外部装
置を駆動する場合はロジック回路側の電源を外部に引出
さないようにするために種にのアイソレート手段が採ら
れる。第1図および第2図は一般的なアイソレート手段
の構成例を示すブロック図であり、・第1図はホトカプ
ラを用いた場合%IJX2rI!Jは絶縁増幅器を用い
た場合を示している。第1図に示す例においてはCPU
  (中央処理装置)lの出力データをラッチ回路2で
ラッチした後、ホトカプラ3を介してD/A 変換器4
へ供給し、D/A変換器4のアナログ出力を増幅器5を
介して外部機器へ供給する。また、8g2図に示す例(
おいては、ラッチ回路2の出方を絶縁増幅器6によって
絶縁増幅した後、増幅器5を介して外部機器へ供給する
When converting the results of calculations by an electronic circuit such as a microcomputer into an analog signal and driving an external device using this analog signal, separate isolation means is required to prevent the power from the logic circuit side from being drawn outside. is taken. Figures 1 and 2 are block diagrams showing examples of the configuration of general isolation means. - Figure 1 shows %IJX2rI! when a photocoupler is used. J shows the case where an isolated amplifier is used. In the example shown in Figure 1, the CPU
(Central processing unit) After the output data of l is latched by the latch circuit 2, it is transferred to the D/A converter 4 via the photocoupler 3.
The analog output of the D/A converter 4 is supplied to external equipment via the amplifier 5. In addition, the example shown in Figure 8g2 (
In this case, the output of the latch circuit 2 is isolated and amplified by the isolation amplifier 6, and then supplied to external equipment via the amplifier 5.

ところで、第1図に示す構成においてはD/A変換器4
の出力信号が小さいため増幅器5を必要とし、また、高
精度にするためには高速のホトカプラを数多く使用しな
ければならず構成が複雑に  −なるとともに高価とな
る欠点がある。次に、第2図に示す構成においては絶縁
増幅−6そのものが高価であるとともに、出力が小さい
、ので増幅器5を必要とする欠点がある。このように、
第1図、第2図に示す構成例においては供に増幅器5を
必要とし、また、との増幅器5を動作させるための電源
を別途に設けなければならないという問題があった。
By the way, in the configuration shown in FIG.
Since the output signal is small, an amplifier 5 is required, and in order to achieve high precision, a large number of high-speed photocouplers must be used, making the configuration complex and expensive. Next, the configuration shown in FIG. 2 has the disadvantage that the isolated amplifier 6 itself is expensive and has a small output, requiring the amplifier 5. in this way,
In the configuration examples shown in FIGS. 1 and 2, there is a problem in that an amplifier 5 is also required, and a power source for operating both amplifiers 5 must be provided separately.

この発明は上述した事情に鑑み大きな出方を取シ出すこ
とができ、しかも、簡単な構成で安価に製作することが
できる絶縁形電流増幅器を提供するもので、一方の入力
端にアナログ信号が供給これる差動増幅器と、との差動
増幅器の出方信号に対応して電流を制御する電流制御素
子と、この電流制御素子の出方電流の向きを交互に切シ
替えてトランスの1次側に供給するスイッチング手段と
、前記トランスの1次側電流を前記差動増幅器の他方の
入力端に帰還する帰還手段とを具備し、前記トランスの
2次電流を余波整流して負荷に供給することを特徴とし
ている。
In view of the above-mentioned circumstances, the present invention provides an isolated current amplifier that can provide a large output and that can be manufactured at low cost with a simple configuration. a current control element that controls the current in response to the output signal of the differential amplifier, and a current control element that alternately switches the direction of the output current of the current control element to control the output current of the transformer. and a feedback means for feeding back the primary side current of the transformer to the other input terminal of the differential amplifier, rectifying the secondary current of the transformer and supplying it to the load. It is characterized by

以下図面を参照してこの発明の実織例について説明する
Examples of actual weaving of the present invention will be described below with reference to the drawings.

第3図はこ9発明の一実施例の構成を示すプロツク図で
あシ、第2図の各部と対応する部分には同一の符号が付
しである。
FIG. 3 is a block diagram showing the structure of one embodiment of the present invention, and parts corresponding to those in FIG. 2 are given the same reference numerals.

この図において8は抵抗9〜12とともに差動増幅器1
3を構成する演算増幅器であり、この演算増幅器8の■
入力端にD/A変換器4のアナログ出力信号S1  が
抵抗9を介して供給される。差動増幅器13の出方信号
はトランジスタ14のペースに供給され、このトランジ
スタ14のコレクタには電源vcc が供給される。ま
た、トランジスタ14のエミッタはトランス15の1次
巻線のセンタータップに接続され、この1次巻線の両端
は各々トランジスタ16.17のコレク゛りに接続され
ている。トランジスタ16.17のエミッタは共(可変
抵抗18の一端に接続され、可変抵抗18の他端は接地
されている。そして、可変抵抗18の摺動端子と接地間
に得られる電圧は演算増幅器8のθλ入力端抵抗11を
介して帰還される。
In this figure, 8 is a differential amplifier 1 along with resistors 9 to 12.
3, and the operational amplifier 8's ■
An analog output signal S1 of the D/A converter 4 is supplied to the input end via a resistor 9. The output signal of the differential amplifier 13 is supplied to the base of a transistor 14, and the collector of this transistor 14 is supplied with the power supply vcc. The emitter of transistor 14 is connected to the center tap of the primary winding of transformer 15, and both ends of this primary winding are connected to the collectors of transistors 16 and 17, respectively. The emitters of the transistors 16 and 17 are both connected to one end of the variable resistor 18, and the other end of the variable resistor 18 is grounded.The voltage obtained between the sliding terminal of the variable resistor 18 and the ground is connected to the operational amplifier 8. It is fed back through the θλ input terminal resistor 11 of .

20は第4図(ハ)に示す矩形の信号s5  とこの信
号S5  を反転した信号S5(同図に))とを出方す
る発振器であシを信号S5 が抵抗21を介してトラン
ジスタ16のペースに、信号S5  が抵抗22を介し
てトランジスタ17のペースに各々供給され、これによ
り、トランジスタ16.17が交互にON −OFF動
作を行うようになっている。また、トランジスタ16.
17%抵抗21.22および発振器20でスイッチング
手段23が構成されている。一方%24は外部機器であ
り、全波整流器25を有している。〜は全波整流器25
の出力端子間に接続される負荷抵抗である。
20 is an oscillator that outputs a rectangular signal s5 shown in FIG. A signal S5 is supplied to each of the transistors 17 through the resistor 22, so that the transistors 16 and 17 are alternately turned on and off. Also, transistor 16.
The switching means 23 is composed of the 17% resistors 21 and 22 and the oscillator 20. On the other hand, %24 is an external device and has a full-wave rectifier 25. ~ is full wave rectifier 25
is the load resistance connected between the output terminals of

上述した構成においてD/A 変換器4から第4図(イ
)に示す信号S1  が出力されると、この信号S□が
差動増幅器13で電圧増幅された後、トランジスタ14
で電流増幅されて信号S2  となる。したがって、第
4図(ロ)に示す信号S2の波形は信号S0と等しくな
る。そして、この信号S2  はトランジスタ16がO
Nの時はトラン;< 、r、 sの1次巻線のセンター
タップ−トランジスタ16→可変抵抗18なる経路で流
れ、また、トランジスタ17がONの時は1次巻線のセ
ンタータップ−トランジスタ1フ→可変抵抗18なる経
路で流れる。したかって、トランジスタ16.17のコ
レクタに流入する電流を各々信号S3.S4  とすれ
ば、信号S  、  S4は各々第4図(ホ)、(へ)
に示すように、信号S2  と同゛じ波形の区間と0レ
ベルの区間とを交互にくり返す信号となる。この結果、
トランス15の2次側出力を全波整流した波形、すなわ
ち、負荷抵抗〜の両端電圧波形はi@4図(ト)に示す
ように信号S1(同図(イ))と同じ波形となる。
In the above configuration, when the signal S1 shown in FIG. 4(a) is output from the D/A converter 4, this signal S
The current is amplified at , and becomes the signal S2. Therefore, the waveform of signal S2 shown in FIG. 4(b) is equal to signal S0. This signal S2 causes the transistor 16 to turn off.
When it is N, the flow follows the path of transformer; The current flows through the path from F to variable resistor 18. Therefore, the currents flowing into the collectors of transistors 16, 17, respectively, are connected to signals S3. S4, the signals S and S4 are shown in Fig. 4 (e) and (e), respectively.
As shown in FIG. 2, the signal is a signal that alternately repeats sections of the same waveform as the signal S2 and sections of 0 level. As a result,
The waveform obtained by full-wave rectification of the secondary side output of the transformer 15, that is, the voltage waveform at both ends of the load resistor ~ has the same waveform as the signal S1 (FIG. 4(A)) as shown in i@4 (G).

なお、上述した構成において、トランジスタ16.17
fr各々ダーリントン接続のトランジスタに代えれば、
ペース電流を少さくし得るので可変抵抗18を流れる電
流と信号S2 の値とが高い精度で一致し、これによシ
、回路動作の高精度化を計ることができる。
Note that in the above configuration, the transistors 16 and 17
If each fr is replaced with a Darlington-connected transistor,
Since the pace current can be reduced, the current flowing through the variable resistor 18 and the value of the signal S2 match with high precision, thereby making it possible to improve the precision of circuit operation.

ま之、この実施例によれば電流増幅を行っているので全
波整流器25における順方向電圧時−下分を補償するこ
とができ、また、トランス15の2次側以降の外部機器
に接触不良があった場合は、2次側電圧が上昇するので
、これにより接触不良を防止する効果を有する。
However, according to this embodiment, since current amplification is performed, it is possible to compensate for the lower part of the forward voltage in the full-wave rectifier 25, and also to prevent poor contact in external equipment after the secondary side of the transformer 15. If this happens, the secondary voltage increases, which has the effect of preventing poor contact.

以上説明したようにこの発明によれば、一方の入力端に
アナログ信号が供給される差動増幅器と。
As explained above, according to the present invention, there is provided a differential amplifier to which an analog signal is supplied to one input terminal.

この差動増幅器の出力信号に対応して電流を制御する電
、流制御素子と、この■、電流制御素子出力電流の向き
を交互に切シ替えてトランスの1次側に供給するスイッ
チング手段と、前記トランスの1次側電流を前記差動増
幅器の他方の入力端に帰還する帰還手段とを具備したの
で、筒車な構成で安価に製作することができるとともに
、大きな出力を取り出し得る利点が得られる。
A current control element that controls the current in response to the output signal of the differential amplifier, and a switching means that alternately switches the direction of the current control element output current and supplies it to the primary side of the transformer. , and a feedback means for feeding back the primary current of the transformer to the other input terminal of the differential amplifier, which has the advantage that it can be manufactured at low cost with an hour wheel configuration and that a large output can be extracted. can get.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は各々従来のアイソレート手段の構成を
示すブロック図、第3図會よこの発“明の一実施例の構
成番示すブロック図、第4図(イ)〜(ト)は各り第3
図に示す回路各部の波形を示す波形図である。 13・・・・・・差動増幅器%14・・・・・・トラン
ジスタ(電流制御素子)、18・・・・・・可変抵抗(
帰還手段)、23・・・・・・スイッチング手段、25
・・・・・・全波整流器。 特開昭59−204305 (3)
1 and 2 are block diagrams showing the configuration of conventional isolation means, FIG. 3 is a block diagram showing the configuration number of an embodiment of the present invention, and FIGS. ) is the third
FIG. 3 is a waveform diagram showing waveforms of various parts of the circuit shown in the figure. 13... Differential amplifier% 14... Transistor (current control element), 18... Variable resistor (
feedback means), 23...switching means, 25
...Full wave rectifier. Japanese Patent Publication No. 59-204305 (3)

Claims (1)

【特許請求の範囲】[Claims] 一方の入力端にアナログ信号が供給される差動増幅器と
、との差動増幅器の出力信号に対応して電流を制御する
電流制御素子と、この電流制御素子の出力電流の向きを
交互に切カ替えてトランスの1次側に供給するスイッチ
ング手段と、前記トランスの1次側電流を前記差動増幅
器の他方の入力端に帰還する帰還手段とを具備し、前記
トランスの2次電流を全波整流して負荷に供給すること
を特徴とする絶縁形電流増幅器。
a differential amplifier to which an analog signal is supplied to one input terminal; a current control element that controls the current in response to the output signal of the differential amplifier; and a current control element that alternately switches the direction of the output current of the current control element. and a feedback means that feeds back the primary side current of the transformer to the other input terminal of the differential amplifier, and includes switching means that supplies the primary side current of the transformer to the other input terminal of the differential amplifier, An isolated current amplifier that rectifies waves and supplies them to the load.
JP58078667A 1983-05-04 1983-05-04 Insulation type current amplifier Pending JPS59204305A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58078667A JPS59204305A (en) 1983-05-04 1983-05-04 Insulation type current amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58078667A JPS59204305A (en) 1983-05-04 1983-05-04 Insulation type current amplifier

Publications (1)

Publication Number Publication Date
JPS59204305A true JPS59204305A (en) 1984-11-19

Family

ID=13668209

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58078667A Pending JPS59204305A (en) 1983-05-04 1983-05-04 Insulation type current amplifier

Country Status (1)

Country Link
JP (1) JPS59204305A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02290312A (en) * 1989-01-12 1990-11-30 Uniphase Corp Information channel and method of signal transmission

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5447462A (en) * 1977-09-21 1979-04-14 Toshiba Corp Dc signal isolator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5447462A (en) * 1977-09-21 1979-04-14 Toshiba Corp Dc signal isolator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02290312A (en) * 1989-01-12 1990-11-30 Uniphase Corp Information channel and method of signal transmission

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