JPS59204277A - Manufacture of metal oxide semiconductor device - Google Patents

Abstract

PURPOSE:To miniaturize the element by reducing the area of the part of an intermediate insulation film by a method wherein the surface of a gate electrode is oxidized after forming the electrode, the part other than the gate forming part is etched, and further the side surface of the gate electrode is thermally oxidized after forming the source and drain. CONSTITUTION:A part of an Si wafer 1 is etched, and a field oxide film 2 is formed by CVD method, etc. Next, after forming a gate oxide film 3 on the wafer 1 by thermal oxidation, the gate electrode 4 is formed. Then, the surface of said electrode 4 is oxidized and thereafter etched by leaving the part serving as the gate. A metal 10 of a chemical potential for oxide formation much lower than that of Si is vapor-deposited, and further the silicide 11 of the metal 10 is formed. The side surface of the electrode 4 is oxidized by thermal oxidation. After selectively removing a metallic oxide 12, wirings 8 of the source and drain electrodes 11 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method of manufacturing an MO8 type semiconductor device that allows the size of an MO8 type transistor element to be reduced.

(Prior Art) A conventional method for manufacturing an MO8 type transistor is shown in FIG. In the conventional method, as shown in FIG. 1(a), a buried type element isolation layer 2 is formed on a silicon wafer 1 by dry etching, oxidation, or the like.

Next, as shown in FIG. 1(b), 200%
After forming the gate oxide film 3 of ~500X, P (phosphorus)
Gate electrode 4 is formed of polycrystalline silicon doped with .

Next, as shown in FIG. 1(e), openings for the source and drain are made and AS ions are implanted into the silicon wafer 1, and the source 5 and drain 6 are formed as shown in FIG. 1(d).◇ Next, as shown in FIG. 1(e), an intermediate insulating film 7 is formed to insulate the source 5, drain 6, and gate electrode 4, and as shown in FIG. A drain electrode 8 is formed.

In this way, an MO8 type transistor was manufactured. The number of elements in LSI increases year by year, but since there is a limit to the size of one chip, it has become necessary to reduce the area of the elements.

That is, the gate electrode 4 and the source or drain electrode 8
The intermediate insulating film 7 for insulation isolation is a silicon gate MO.
This makes it difficult to reduce the S transistor element area.

(Object of the Invention) The present invention was made to eliminate the above-mentioned conventional drawbacks, and an object of the present invention is to provide a method for manufacturing an MO3 type semiconductor device that can reduce the device area.

(Structure of the Invention) A method for manufacturing an MO8 type semiconductor device of the present invention includes forming a field oxide film on a semiconductor substrate, performing thermal oxidation to form a gate oxide film, and forming a gate electrode on the gate oxide film. After that, the surface is oxidized and etched leaving a part that will become the gate, then metal is deposited on the entire surface, and ions are implanted at the interface between the metal and the semiconductor substrate and annealed to form the source and drain. Then, the metal in contact with the semiconductor substrate is silicided to form source/drain electrodes, and the sides of the gate electrode are thermally oxidized and the deposited metal is selectively removed to wire the source/drain electrodes. This is what I did.

(Example) Hereinafter, an example of the method for manufacturing an MO8 type semiconductor device of the present invention will be described based on the drawings. FIG. 2(a) to FIG. 2 □□□) are process explanatory diagrams of one embodiment. In this figure 2 (a) to figure 2 (b)), figure 1 (a)
- The same parts as in FIG. 1(f) will be described with the same reference numerals.

First, as shown in FIG. 2(a), a part of the silicon wafer 1 as a semiconductor substrate is etched by photolithography, and the etched areas are etched by CVD, thermal oxidation, etc. for device isolation. Field oxide film 2 50
00-1oooo is formed.

Next, as shown in FIG. 2(b), thermal oxidation is performed at 950 to 1000 DEG C. to form a gate oxide film 3 with a size of 200 to 500 on the silicon wafer 1. Next, 2000-400
0 gate electrodes 4 are formed. As the gate electrode 4, phosphorus-doped polycrystalline silicon, molybdenum, or tungsten silicide is used. Next, in the case of silicide, annealing is performed at 1000°C.

Next, the surface of the gate electrode 40 is oxidized, and the silicides of molybdenum and tungsten become silicon dioxide 14 like polycrystalline silicon. 100 to 200 of these oxides 14 are formed by thermal oxidation at around 950°C.

Next, as shown in FIG. 2(C), resist is left on the part that will become the gate by photo-roughing, and the oxide 14 is
, gate electrode 4 and gate oxide film 3 are etched in this order.

In this case, since the oxide film 14 is on the gate electrode 4, it is undercut, as shown in FIG. 2(C).

Next, as shown in Fig. 2(d), metals 10, such as hafnium and zirconium, whose chemical potential for oxide formation is much lower than that of silicon, are
Deposit about the same amount as a person.

In this case, if the vapor deposition is performed using an electron beam or a snow ivy, the step coverage is not good, so it is difficult to adhere to the side surfaces of the step, and if the gate electrode 4 is undercut, the gate electrode 4 and metal 10 do not come into contact with each other.

Next, As ions were implanted at a rate of 1016/l so as to have a peak at the interface between the metal 10 and the silicon wafer base 1, and annealing was performed in nitrogen at 600 to 1000 DEG C.').

Through this annealing, a silicidation reaction occurs in the portion where the metal 10 is in direct contact with the silicon wafer 1, and as shown in FIG. 2(f), the silicide 11 of the metal 10
is formed.

This silicide generally undergoes volumetric contraction, as shown in Figure 2(f).
As a result, the gate electrode 4 and the metal 10 do not come into contact with each other even after subsequent steps.

In addition, the implanted AS migrates to the interface between the silicide 11 and silicon wafer 1 through a silicidation reaction, so a high concentration As layer is formed under the silicide 11.
They become a source 5 and a drain 6. Further, the silicide 11 becomes a source/drain electrode.

Next, oxidation is performed at 900-1000°C. In this case, the materials of the gate electrode 4 are polycrystalline silicon, tungsten silicide, and molybdenum silicide, and since the oxides are all silicon dioxide, the side surfaces of the gate electrode 4 are The oxide 13 is silicon dioxide, and the thickness of this oxide film is 50 to 200 mm.

In addition, the metal 10 is oxidized, and the oxide 1 of the metal 10 is
2. Also, in the silicide 11, since the chemical potential of the oxide of the metal 10 is lower than that of silicon, the same oxide 12 as in the case of the metal 10 is formed. Through this process, the entire surface of the gate electrode 4 is surrounded by silicon dioxide 3, 13, 14 and insulated from the others.

Next, the metal oxide 12 is selectively removed and the metal 10 is removed.
Then, as shown in FIG. 2(g), the wiring 8 of the source/drain electrodes 11 is formed and a transistor is fabricated.

As explained above, the first embodiment eliminates the step of forming an intermediate insulating film, compared to the conventional method. This intermediate insulating film had to remain approximately 1 to 3 μm thick due to mask alignment accuracy.

This first embodiment uses thermal oxidation instead of the intermediate insulating film, and since this oxide film has a thickness of about 50 to 200,
The area of the intermediate insulating film can be reduced.

Further, the insulation of the gate electrode 4 is entirely silicon dioxide, which is a good insulator.

(Effects of the Invention) As described above, according to the method of manufacturing an MO8 type semiconductor device of the present invention, the sidewalls of the gate electrode are thermally oxidized to form an oxide, so an intermediate insulating film is not required. . Accordingly, the element area can be reduced and it can be used in the manufacturing process of VLSI with MO8 structure.

[Brief explanation of drawings]

FIGS. 1(a) to 1(f) are process explanatory diagrams for explaining a conventional method of manufacturing a MOS transistor, and FIGS. 2(a) to 2(g) are MO8W semiconductors of the present invention. FIG. 3 is a process explanatory diagram illustrating an example of a method for manufacturing the device. 1... Silicon substrate, 2... Field oxide film, 3
... Gate oxide film, 4... Gate electrode, 5... Source, 6... Drain, 8... Source/drain electrode, 10... Metal, 11... Source/drain electrode, 12...Oxide of metal 10, 13...Silicon dioxide on the side surface of the gate electrode, 14...Silicon dioxide O on the upper part of the gate electrode. (e) (f) (C1)

Claims (1)

[Claims] forming a field oxide film on the semiconductor substrate and then performing thermal oxidation to form a gate oxide film on the semiconductor substrate;
A step of forming a gate electrode on the gate oxide film, oxidizing its surface, etching it leaving a portion that will become the gate, and then vapor depositing metal on the entire surface, and implanting ions into the interface between the metal and the semiconductor substrate. a step of forming a source/drain by annealing and siliciding the metal in contact with the semiconductor substrate to form a source/drain electrode; and a step of thermally oxidizing the side surface of the gate electrode and removing the vapor-deposited metal. A method of manufacturing an MO3 type semiconductor device that is similar to the process of selectively removing and wiring source/drain electrodes.