JPS59200522A - A/d converter - Google Patents

Abstract

PURPOSE:To secure reliability higher than a specific level by providing plural A/D converters and a logical means which selects a signal with high accuracy of quantization among plural quantized signals. CONSTITUTION:Plural A/D converters 2 each consisting of a sampling and holding circuit parts 2a and a quantizing circuit part 2b are provided. Further, the logical circuit part 3 outputs a single signal with high accuracy selectively among plural quantized signals (1)-(N). Furthermore, a fault diagnostic part 4 for monitoring the reliability of each A/D converter 2 is added. This system discards automatically the output of a converter which causes an error in quantization, so quantization is performed with higher accuracy than the case where a single A/D converter is used. Thus, reliability higher than the specific level is secured even when a faulty converter coexists.

Description

[Detailed Description of the Invention] Technical Field> As the digitalization of audio and video products in consumer and home appliances rapidly progresses, the accuracy or reliability of A/D conversion, which converts analog input signals to digital signals, is becoming increasingly important. It has come to have extremely important meaning. That is, it can be said that only when high reliability is guaranteed in the conversion part of the human input signal, the functions of the various signal processing systems and output sections that follow can be effectively utilized. The A/D conversion device of the present invention includes voice analysis and recognition 1
It can be used not only as an input section of a synthesis device or an image recognition/reproduction device, but also as an input section of digital audio/video equipment in general, and as an input section of a measuring device such as a digital multimeter.

<Background of the Invention, Prior Art> The audio band that human hearing can discern is at most 20 KHz, and in this case, the sampling frequency of analog signals defined by the Nyquist theorem is 40 KHz. Even if you want to make the sound quality of digitally processed audio band signals as high as possible, the sampling frequency is at most 100.
up to KHz. On the other hand, current image processing focuses on processing still images or semi-still images that do not require real-time processing.
In order to obtain a quantized signal equivalent to 256×256 pixels during period z), a sampling frequency of approximately 7 MHz is required.

Although the sampling rate remains in the relatively slow to medium speed range, the sound quality is high.

In order to pursue image quality, it is necessary to expand the dynamic range, that is, increase the number of quantization bits. However, the current converter that quantizes analog input signals usually uses only a single A/D converter, and the hold circuit that latches the input signal as an analog signal may deteriorate over time and the hold capacitor may deteriorate. Failure due to insulation breakdown,
The quantization accuracy, which takes into account deterioration of characteristics over time of the digitizing circuit unit that quantizes the latch signal, is not clear, and it is difficult to say that the reliability is high. The result of sampling using such a low-reliability A/D converter is that, contrary to the intention of expanding the dynamic range, it is difficult to maintain the quality of sound quality 2 image quality at a certain level due to bit loss etc. .

In particular, in the field of image processing where the number of quantization bits is relatively small due to processing speed constraints, the quantization error is specified for the full scale of the analog input signal. Inaccuracies in quantization that appear as such are fatal as they result in incorrect digital image information being sent to the processing system. Furthermore, in digital signal processing that assumes a relatively strong correlation between adjacent sample signal values, for example, delta modulation, D P CM (D
iferential Pulse Code Mo
duration).

When encoding quantized data using various PCM methods such as the linear prediction method, characteristic instability due to changes in the A/D converter over time leads to a decrease in encoding accuracy due to quantization errors and reflects incorrect correlation. This will provide the output information.

FIG. 1 shows an example of a conventional quantization method using a single A/D converter and quantization errors that may occur in that case. Input sampling begins in the sample and hold circuit section from the falling edge of the sampling clock, and reaches the launch level after an acquisition time (tacq). At this time, the latch level includes an error corresponding to the gain error (ΔVG) with respect to the input signal level to be held. The latched analog signal is converted into a digital signal by the quantization circuit, but during the period ("conv") required for conversion,
The latch signal level causes a level drop (ΔVD) due to leakage current of the hold capacitor.

As described above, the reliability of conventional A/D conversion is greatly influenced by the droop rate l defined as (gain error ΔvG and ratio ΔVI of drop due to leakage current and conversion period)/1conv. In particular, when the capacitance of the hold capacitor is reduced for high-speed conversion, the droop rate increases logarithmically, and due to the minimum time required for digitization, ΔvG + ΔVD > ΔV (LSB), and the quantized lower bits, especially the LSB bits. There is a high possibility that bits will be dropped (the shaded area in FIG. 1 indicates bits that are missing).

Alternatively, the droop rate may fluctuate, especially increase, depending on the hold signal level due to deterioration in the characteristics of the comparator or hold capacitor in the hold circuit, or poor offset adjustment. Bit loss appears.

As described above, with current A/D converters, it is not possible to evaluate the reliability of the input section including the A/D converter itself, that is, it is not possible to detect quantization errors, and even more so when an error occurs. No measures have been taken to provide relief.

<Objective of the Invention> The present invention enables an A/D conversion device to evaluate its reliability, guarantees reliability of a certain level or higher even if there are defective converters, and directly detects defective parts. The purpose of the present invention is to provide a converting device that can be identified.

<Embodiment> FIG. 2 shows a system configuration that can perform data collection by sampling and data conversion from analog signals such as audio band and image input with high reliability. The system is characterized by having a plurality of coupling systems (A/D converters) 2 each consisting of a sample-and-hold circuit section 2a and a quantization circuit section 2 (+), and also by providing a highly accurate single signal from a plurality of quantized signals. It has an appropriate logic circuit section 3 for selectively outputting signals, and is further equipped with a fault diagnosis section 4 for monitoring the reliability of the plurality of A/D converters 2, 2... I can point out that However, FIG. 2 shows the case of M-bit quantization and lower m-bit diagnosis. Further, the analog input signal is input to each A/D converter 2 through a low-pass filter 1.

In such a system, characteristics deterioration or instability of each A/D converter 2 due to changes over time etc. vary depending on the product, and the failure time of each A/D converter 2 cannot be determined, so each converter Introducing a quantity such as the quantization error rate to It can be evaluated on this basis. In addition, in the above system, the output of the converter that made a quantization error is automatically ignored, so
Compared to using a single A/D converter as in the past,
Highly accurate quantization can be achieved.

Note that the function of the fault diagnosis section 4 is to count the degree of coincidence or mismatch of specific bits of a plurality of quantized signal values, especially the LSB. If we examine the number of times each discrepancy distribution pattern occurs for a certain number of sample data, we can find out the number of converters with noticeable deterioration and the approximate value of their quantization error rate from consideration based on probability theory. .

As shown in ``2'' below, by using a multi-parallel sampling method using multiple converters, even if there are defective converters mixed in, reliability above a certain level can be ensured, and it is possible to identify defective products. You can obtain enough information for 6.

A specific example will be explained in more detail below.

4-bit quantization using three A/D converters consisting of a sample-and-hold circuit section and a sequential comparison type quantization circuit section or a quantization circuit section using a double integral method, and employing majority logic as the selection logic. An example of a system configuration for realizing this is shown in Figure 3.

The analog input signal is limited to a band below the Nyquist frequency (twice the sampling frequency) by a low-pass filter (LPF) to prevent aliasing. A/
D converter 2, 2.2 (+).

+2. In reference 8), 4-bit quantization is performed independently for three sets using a common sampling clock.

In the selection logic circuit section 3, three quantized signals Q11+Q2i+Q3 are generated for each bit from LSB to MSB.
i (i=o, I, 2.3) is input to the majority logic circuit Bi. In this embodiment, since fault diagnosis is performed only on the LSH of the quantized signal, a circuit having a function of comparing and detecting coincidence of two human input signal levels as shown in FIG. 4(a) is used as the BO. For the upper focus numbers of LSB, the 4th
A simplified circuit as shown in Figure (b) is used as B1-B5.

The mismatch detection signals F1 to F3 in FIG. 4 (al) are
A/D converter pair (2, 3), (+3, 1)
), and (1.+2) become "High" when one A/D converter causes a quantization error. The failure diagnosis unit 4 in FIG. 3 counts and displays the number of discrepancies in "-" by 2.

In this embodiment, a 10-bit asynchronous counter C0UNTI
Using ~C0UNT8, each quantizer pair is 1024
It is possible to count the number of mismatches up to times.

This is a necessary condition in the worst case for quantization errors to be repaired by majority logic when the number of sample data is set at 2048. 3 of the number of discrepancies detected above
From the distribution for the set of quantizer pairs, a defective converter can be identified, and an approximate value of the LSB quantization rate of the converter and the LSB quantization accuracy based on majority selection logic can be estimated.

If the weight of the following (Moon uses 3 A/D converters and the full scale of the input signal]/2 LSB is relatively large, then the above (Il uses 5 A/D converters) When used, (IIT) is the full scale of the input signal (1/
When the weight of 2LSH is relatively small and it is necessary to evaluate the quantization accuracy for the lower 2 bits of LSB (Bo) and the next upper pitch 1-(B,), Each diagnosis is explained.

(I) 1/2 of the full scale of the input signal
If the weight of the LSB is relatively large, consider that all the upper bits except the LSB in the three A/D converter numbers are quantized with an accuracy close to 100%.
Only when this happens is the quantization accuracy as a system calculated from the quantization error rate of each converter.

The theoretical basis supporting reliability is outlined below.

Generally, the LSB quantization error rate in three quantizers is expressed as Pl , P2 , Pg (o≦P3 ≦P2≦P1
≦1), Pl -P, P2-P(1-α), Pg = P
(+-/8).

0≦P≦1, 0≦α≦β≦1 It stands out.

(I) When all three quantizers perform normal quantization; the probability is 53-(1-Pl)(1-P2)(1-Pg)-(1-
P)”+(α+β)P(1-p)2+αβP2(1-
P)・・・・・・・・・(11 1I) If two out of three quantizers perform quantization correctly and the remaining one makes a quantization error; the probability is 52=(+−P ,XI-P2)P3+(1-P, )P
2 (1-Pg) 10P, (+-P2) (+-P3) -3 (+-P) P+ (α monk) P (+-P) (3P-
1)" (βP2(sp-2) ...... (2) (iii) When two out of three quantizers make quantization errors and only the remaining one quantizes correctly. ;Probability is F2=P, P2 (+ -Pg)10P, (+
-P2)P3+(IPI)P2P3-3 (]
-P )p2-(2(α-+-l/)-αβ)(+-P
)P2+(@+/j)-2αβ)Pg ・・・・・・(3) (iii) When all three quantizers make quantization errors; the probability is F3-PIP2P3-P3(+ -α) (1-β) mountain... (4) The phenomenon of performing multiple quantization in parallel in one sampling using three A/D converters is the above (1) to ( In other words, S3+520F2-1-F33l.

By the way, the degree of progress of characteristic deterioration of the three converters is as follows:
Characterized by type of species.

(a+ Characteristic deterioration is noticeable only in one specific converter,
The remaining two converters are almost normal (b) Two specific converters are degraded to almost the same degree, but the remaining one is almost normal (c) All three converters are to the same degree The degree of progress of such characteristic deterioration is shown, for example, in Figure 5 (
It is expressed as a) to (c). (a) to (c) shown in the diagram
) corresponds to the above types (a) to (c). For these model types, it would be more realistic to represent the model in Figure 6 (a+ or (bl).
In the case of Figure (a), the model type (bl) is the worst case number, and in the case of Figure 6 (b), the model type (c+) is the worst case number. Quantitative discussions are provided for each model type (a),
Perform each step (b) and (C).

When using majority logic, the quantization accuracy S is 5-83+S
2 ...... (5) It is expressed as. S3, S2 defined by each type (f++, +2) equation, and S given by equation (5), are expressed as LS
B! When expressed as a function of the childization error rate P, it can be summarized as shown in Table 1. To illustrate them, Fig. 7(a) to (C)
becomes.

Table 1 Quantization accuracy as a function of quantization error rate +4-1-P Quantization accuracy according to single A/D converter number (for LSB) Table 1 and Figure 7 (a)
As is clear from the above, model type (a) guarantees 100% reliability by majority logic. That is, even if one specific converter deteriorates, the selected quantization signal is 100% correct as long as the remaining two converters are normal, regardless of its quantization error rate.

In Fig. 7 (bl and (C), quantization accuracy is included -1-P when only one A/D converter is used. (6)
is also indicated with a dotted line. Comparing S and thread, Figure 7 (
bl, that is, model type fbl, does not depend on the LSB quantum quantization rate and always holds: S>identification, (PX3, 1). Therefore, the accuracy of quantization is improved compared to the usual case where one A/D converter is used. For example, when P=1/2, the quantization accuracy is 50% to 75%.
% (This increases by 1.5 times.

Next, in model type (c), as shown in Figure 7(c), when 0<P<1/2, S>2° and when P=1/2, S-T.

When 1/2<P<+, S<4°. In other words, if the quantization error rates of the three converters equally exceed 1/2, the quantization accuracy will rather decrease, and it can be said that it is inappropriate to use majority logic as the selection logic.

But here, (3).

F2 defined by formula (4). By F3, F=F2+
F3 (-1-3)... When (7) is defined, F is nothing but the quantization accuracy when using majority logic. In model type (C), the quantization accuracy S in the majority logic and the accuracy F in the majority logic expressed as a function of the quantization error rate P in three converters are shown in FIG.

In this case, switching between majority logic and majority logic is the fourth
This can be easily implemented by simply inverting the output signal Q from the majority logic circuit in FIG. All you need to do is add a selection logic switching circuit.However, as a practical matter, the information from the fault diagnosis section 4 shown in Figs. If it is determined that the
By replacing all converters and continuing to use majority logic, higher quantization accuracy can be expected than with majority logic.

This is because all three have deteriorated, and all have error rates closer to 1 than 1/2, and the three replaced unused ones are all degraded with an error rate of 1/2 or higher. This is because the furnace room is extremely crowded. Quantitatively speaking, if the quantization error rates before and after exchange are Po1d and Pnew, then the number is clear from FIG. If ew(] −Pold, then F(P=
This is because the relationship Pold)<S (P=Pnew) holds true, and in this case, the relationship between Pnew and Pold can easily satisfy the condition 1.

Next, L S when using five A/D converters
B Check the quantization accuracy. If we consider exactly the same way as when using three A/D converters and use majority logic, we get:
In the worst case where all five A/D converters deteriorate to the same degree, the results shown in FIG. 10 are obtained. Quantization error rate P or 1/
In a range smaller than 2, the accuracy is further improved by about 10% at most than when three A/D converters are used.

When P exceeds 1/2, by switching the selection logic to the majority logic, the same quantization accuracy as when replacing P→I −PI in the majority logic can be obtained.

The circuit configuration of this example uses the five-man power majority logic circuit (with a match detection function) shown in FIG. 11(a) as the BO in block 3 of FIG. 3, and the circuit shown in FIG.
This is realized using a simplified circuit of bl. If necessary, a selection logic switching circuit (FIG. 9) can be added to the output side of the LSB BO to perform majority decision and majority decision logic switching. Note that, as shown in FIG. 11(a), the match detection in the BO can be performed by simplifying the detection to 5 sets without performing the match detection for all 10 matches. Therefore, the number of monitor counters C0UNT in block 41 in FIG. 3 only needs to be five.

@) Considering the case where the weight of /2LSB relative to the full scale of the input signal is relatively small, and it is necessary to evaluate the quantization accuracy for the lower two bits, including the LSB (Bo) and the next higher bit (Bl). do. If we limit external failure diagnosis to LSB and do not monitor B1,
The system configuration when using three A/D converters is the third one.
It is the same as shown in the figure. (Similar to the moon, quantitative evaluation of reliability is performed probabilistically.

Now, for each bit of Bo, B, three A/D
The maximum quantization error rate in converter 2 (lj, 412.41=3) is P and ap (0≦a≦1), respectively.
shall be. The event of performing parallel multiple quantization in one sampling using three converters is as follows when the quantization accuracy of the upper two bits, that is, B2 and B3, is considered to be 100%. It belongs to any one of () to (song).

(1) When all three converters perform normal quantization for the two bits of B, , Bo; probability 531i1 B,
, if there is one converter out of three that causes a quantization error with respect to at least one bit of B, , Bo; probability S2 (Machi) If there are 2 out of 3; probability F2 (iii) If all three converters make a quantization error with respect to at least one bit of B, , Bo; probability F3 Here, as in CI+, S3+82-1-F2-7F3
It is 31.

The quantization accuracy for the lower two bits when using majority logic or minority logic, that is, the probability that both Bo and B1 will be correctly quantized, is given by (5) Equation S or (same as the moon), respectively.
7) It can be defined by formula F.

The degree of progress of characteristic deterioration of the three converters is expressed as (I
It is similarly characterized by the model types (a) to (c) mentioned above. Therefore, there are nine types of model types for characteristic deterioration of the converter regarding the lower two bits, but for the sake of simplicity, we will introduce three model types (al to (c) shown in FIGS. 12(a) to (c)). Consider only C).The solid line is B.

(LSB) quantization error rate, and the broken line is the quantization error rate of B1. Although not shown in the figures, both types include not only cases in which 2-bit quantization errors occur in the same converter, but also cases in which 2-bit quantization errors occur across different quantizer numbers. In other words, this includes the case where a converter that causes a quantization error regarding LSH correctly quantizes its upper bits, and the exact opposite case. Model type (a) has 2 normal and 1 degraded for every 3 converter bits, model type (b) has 1 normal and 2 degraded for every 3 quantizer bits. If the model type (
C) is the case of 3 degradations for every 3 converter bits.

Quantization accuracy S when using B3, B2 and majority logic, LSB quantization error rate P, and B.

and B1 as a function of the load ratio a can be summarized as shown in Table 2. These are illustrated in Figures 13(a) to (
It becomes C1.

Tray 1 [゛Table 2 Quantization error rate and B. and B1 O -(1-a
P) (1-PX-"B3); as a function of the weight ratio ・Single-A/D converter conversion accuracy
Quantization accuracy (lower 2 bits BO and Bl **l
≦Pa<], with sJ (getting stuck)
As is clear from Table 2 and FIG. 13(a), model type (a) guarantees 100% reliability by majority logic. On the other hand, the quantization accuracy for the lower bits when only a single A/D converter is used is -(1-a P ) (+ -P ) ---f3)
Therefore, in type (a), it is nothing but B3-,S. Figure 13 (as shown in al., for example, a
= 1/2, P = t/2, the conventional single quantization scheme has a reliability of just under 40%. In this way, the effect of simultaneous multiple quantization is extremely large.

When a = 0 in Figures 13 (a) to (c), Figure 7 F, which shows the quantization accuracy of only the LSB, ignoring B1 (quantization accuracy is 100 fo), do.

In Figure 13 (bl and (C)), the curve for N=1 is (8)
4 of Eq. In model type (b) (see FIG. 14), S>2. (P(o, t). For example, when the quantization error rates of Bo and B1 are equal, that is, when a = 1, the quantization accuracy will increase from 25% to 56% by approximately 2 Next, in model type (C), which is the worst case of type (a) and (bl, there is a S-included Pa in the range l/2<P<1, and 0< For P < Pa, S> recognition, pa (for P < 1, S < 2, (when a-0 or 1, Pa = 1 / 2
It is. ). Therefore, with three converters, the quantization error rate is P
If the error rate does not exceed a, the majority logic is effective, but if the error rate exceeds Pa, the reliability will not decrease if the quantization accuracy F based on the minority logic defined by equation (7) is adopted.

In either case, the quantization accuracy is improved by a maximum of about 1.2 times compared to when a single converter is used. B in block 3 of FIG. 3 if it is desired to switch the selection logic. ,B.

The circuit shown in FIG. 9 may be added to the output side of the circuit.

Note that, as is clear from the above discussion, it is not necessary to provide a majority selection logic circuit corresponding to each bit as in the embodiment. For example, if you provide only the corresponding part (B for the moon and B1 for the town), you can quantize with a predetermined accuracy. Alternatively, in order to use it in correspondence with any range, it is appropriate to configure it as in the embodiment.

In case of mismatch detection (fault diagnosis is performed using three A/D converters), model types (a) to
) based on the discussion.

When the number of mismatches in the A/D converter pairs is counted from the mismatch detection signals F1 to F3 in FIG. 4(a) and the distribution pattern is examined, Table 3 shows.

Here, ◎ indicates a case where both quantization results are correct and match, and ◎ indicates a case where both results are incorrect and match. Further, x represents a case of mismatch in which one quantization result is correct and the other is incorrect.

For each model type, the expected number of mismatch detections is
When normalized by the number of sample data, □-P
...Song... (9) M=2P(+-P)
It is expressed in two types (10) (see Figure 14), and is distributed as shown in Table 4.

Here, P is the LSB quantum quantization rate. As is clear from Table 4, the number of mismatch detections shows a unique distribution pattern for each model type.
), there are always two normal converters, so there are unmatched pairs that are not detected. The remaining two pairs have the same number of mismatches, m.

(11) In model type (b), there are always two converters that make quantization errors, so there are two pairs that include a converter with significant characteristic deterioration, and the number of mismatch detections is equal to m. be. The remaining pair has a mismatch count of M.

(Town) In model type (C), the three converter pairs are completely equivalent, so the number of mismatches is equal M.

From the results of consideration of (I) to (Iff+) mentioned above, L'S
It can be seen that when the B quantization error rate P exceeds 215, reliability can be improved even by the multiple quantization method employing majority logic. Therefore, it can be said that failure diagnosis becomes important in the range of P≧215.

From formula (lO) or Figure 14, 0<P<+, M≦1/2, m<1/
2.

Since 1/2<P<+ and m>1/2°, if the counting result of the number of discrepancies exceeds half of the number of sample data and an overflow display appears, the error rate P of one or two converters will increase. can be determined to be 1/2 or more. In this case, if there is one pair of converters for which the number of mismatch detections is extremely small, the model type (ali) is close, that is, the two converters in the pair are almost normal, and the remaining one is a type with significant deterioration. Otherwise, a considerable discrepancy will be detected in two pairs of transducers containing two significantly degraded transducers (however, not more than half of the sample data).In other words, model type (b ) belongs to a type similar to

When the error rate P is close to 1/2, it is difficult to determine whether the failure situation is close to the model type (bl or (C). However, assuming the worst case type tc+, all three converters It would be appropriate to treat this by considering that the deterioration is significant.However, in the case of model tie-% (for l, the error rate is P'' and l-P''), the number of mismatch detections is equal, so P is 1.
It is necessary to determine whether it is larger or smaller than /2. In that case, it is difficult to imagine that a quantization error due to an initial failure will occur with a probability of 1/2 or more for all three A/D converters. Therefore, errors due to initial defects that are unrelated to characteristic deterioration due to changes over time are P < 1 /
It can be said that 2. On the other hand, in the case of changes over time, the failure situation should gradually shift from a type close to model fa) to type (C) due to characteristic variations in each A/D converter, and The value of P can be estimated from the absolute value of the number of mismatches m. That is, type (c)
The error rate in is never less than the estimate of P in type (bl).

The criteria for identifying a defective converter when the LSB quantum quantization rate can be determined to be 1/2 or more based on the failure diagnosis information number has been shown above. When the error rate is less than 1/2,
A quantization accuracy of 50% or more is guaranteed by majority logic, and monitoring for fault diagnosis has the meaning of sequentially tracing changes over time.

<Effects of the Invention> As described in the previous sections, the present device has (1) a quantization accuracy of 50% or more even in the worst case.

(iil it quantization accuracy can be improved by increasing the number of A/D converters.

(Machi) It is possible to identify A/D converters whose quantization error rate exceeds 1/2 and whose characteristics have significantly deteriorated.

As a result, the present invention can be applied to various application fields requiring high reliability with a simple circuit configuration.

In the areas of speech recognition and pattern recognition, source data for digital processing can be generated with high reliability.
This will give high quality processing results. Furthermore, this method is extremely effective especially in the field of measuring instruments where reliability is a critical issue.

[Brief explanation of the drawing]

FIG. 1 is a time chart explaining errors in the quantization process, FIG. 2 is a basic system configuration diagram showing an embodiment of the present invention, and FIG. 3 is a system configuration diagram showing a specific example of the same.
FIGS. 4(a) and 4(b) are block diagrams showing details of the main parts of FIG. 3, FIG. Figure 6 (a) (bl is a diagram showing a realistic degree of progress compared to Figure 5, Figure 7 (,
) (bl(C) is a diagram explaining LSB quantum quantization accuracy versus weight, Figure 8 is a diagram explaining LSB quantum quantization accuracy versus weight using decimal logic, and Figure 9 is a specific example (selection logic in this A block diagram showing the switching circuit, FIG. 10 is a diagram explaining LSB quantization accuracy based on majority logic, and FIG. 11(a) (
b) is a diagram explaining other specific implementation bits, the first
3(a), (b), and (c) are diagrams for explaining the lower two bit quantization accuracy versus error rate, and FIG. 14 is a diagram for explaining the SB quantization error rate versus the expected rate of mismatch detection times. 2.A/D converter, 3..Selection logic circuit, BQ~B3
...Majority logic circuit. Agent Patent Attorney Aihiko Fukushi (2 people) --~ 1 ~ Grab dfi 20 8 (No. d Prefecture 9th No. 13 + (C) 0 0.5
7 PLSB Tatami J4-14i Tsu @/4 U+

Claims (1)

[Claims] 1. An A/D converter that samples an analog input signal and quantizes it as a digital signal (herein, means for parallel sampling and parallel latching using a single sampling clock using a plurality of sample-and-hold circuits; It is characterized by comprising means for quantizing each analog latch signal into a digital signal, and logic means for selecting a signal with high quantization accuracy from a plurality of quantized signals obtained as outputs of the quantization means. A to do
/D conversion device.