JPH113486A - Battery voltage data transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transmit voltage data without dropping an information transmission speed even if a redundant bit for error control is added by compressing sending data. SOLUTION: An output code of an A/D converter 3 is added to a register 4 and accumulated for one step time of sweep, and the output code is subtracted from an input code of the register 4 through a subtracter 5. Because a subtracting signal is always delayed by only one step time from a subtracted signal, a voltage code in each cell successively appears in an output of the subtracter 5 from the least cell to a higher direction. The output of the subtracter 5 is added to a subtracter 6 and here, an output code of a register 8 is subtracted. The register 8 sequentially makes a note of data of each cell which is sent from the subtracter 5 in a previous timing. The subtracter 6 calculates the difference between of the preceding data from the register 8 and new data from the subtracter 5 in each cell. When difference exists, the register 8 accumulates it as new data to which the difference is added with an adder 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a technique for compressing a data amount suitable for transmitting the voltage data when the battery voltage is monitored at a place remote from the battery.

[0002]

2. Description of the Related Art In general, batteries are often used by being connected in series in multiple stages. In the case of a secondary battery, it is necessary to charge it when it is discharged to some extent. However, individual batteries have variations in charge characteristics and discharge characteristics for each unit. Therefore, it is necessary to constantly monitor the voltage of all batteries.

In the prior art, a voltage monitor for an individual battery has a charge completion voltage of 1.1 times the nominal voltage and a required measurement resolution of 1/100 of the nominal voltage.
To represent this with a digital code, at least 7 bits are required. Therefore, in this case, it is necessary to convert the data into a digital code by a 7-bit A / D (analog to digital) converter and transmit the digital code to all the batteries in a multistage configuration.

[0004]

As described above, in the prior art, when the measurement accuracy is 1/100 of the nominal voltage,
A code having a minimum of 7 bits must be transmitted, but if an error correction code is used to increase the reliability of the transmitted code, it is necessary to use a self-correction code when there is no return line. The code length becomes about twice, and even if there is a return line, the code length increases by several tens of percent. Therefore, for each of the aforementioned batteries,
If the voltage data is transmitted, if the number of stages is large, the time required for the number of stages is required and the code length is increased, so that the time required to cycle through all the batteries is increased. Therefore, the sampling time interval for each battery becomes long.

It is therefore an object of the present invention to find a method that does not require a long sampling time interval for each battery by compressing transmission data even if redundant bits for error correction are added.

[0006]

According to the battery voltage data transmission method of the present invention, the transmitting section subtracts the previous voltage data code stored in the accumulator from the voltage data code sampled and taken out. By transmitting the difference and adding the difference to the voltage data code stored in the accumulator, the content of the accumulator is updated to the latest data code. The receiving unit has an accumulator having the same configuration as the transmitting unit, obtains the latest data code by adding the transmitted difference data to the previous voltage data code stored in the accumulator, and obtains the contents of the accumulator. Update to the latest data code. By using such means, transmission data can be compressed and transmitted.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Although there is a difference depending on the type of battery,
Here, for simplicity, the charge completion voltage is set to a nominal voltage of 1.1.
Assuming that the discharge end voltage is 0.9 times the nominal voltage, the battery voltage fluctuates between these two voltages during charging and discharging.
If each battery transmits only the difference from the previous sample value, rather than transmitting the voltage data, that is, the sample value as it is, at each sampling, the data amount will be considered from the battery voltage change speed. It is clear that is significantly reduced. For simplicity, it is assumed that the discharge characteristics drop linearly from 1.1 times the voltage to 0.9 times the voltage over 8 hours, and the sampling is performed every other minute even if the sampling is performed every other minute. By this time only 1/2400 of the nominal voltage will work. Therefore, assuming that a 7-bit A / D converter is used, the resolution is 1/28, so that the difference between the sample values continues 0 times 18 times, and -1 appears at the 19th. Assuming that the charging characteristics also increase linearly over 8 hours,
The +1 will come out first. Actually, the charging / discharging characteristics are not linear, and vary depending on the type of battery, charging method, and discharging method. For example, even if this slope is eight times the slope at the 8-hour rate, +1 or -1 should be sent once every 2.3 minutes on average. Assuming that the transmission speed of the amount of information to be transmitted is sufficient, the three states of +1, 0, and -1 only need to be expressed. Therefore, the number of bits only needs to be 2 bits. , The data was compressed to 1 / 3.5. By doing so, the transmission data can be compressed, so that even if redundant bits for error correction are added, the sampling time interval for each battery does not increase, and the voltage can be reduced without reducing the information transmission speed. Data can be transmitted. Further, a small-sized voltage data transmission circuit having a simple structure can be formed.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the principle and embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram for explaining a battery voltage data transmission system according to the present invention. In FIG. 1, reference numeral 1 denotes a module composed of a series-connected battery whose voltage is measured, 2 SCN denotes a sweep type selection circuit, and 3 A / D
Is an analog-to-digital converter, 4 REG is a register, 5 and 6 are subtractors, 7 is an adder, 8 REG is a register, 9 CPG is a control pulse generator, 10 ENC is an encoder, and 11 is transmission Line, 12 DEC is the decoder, 13
CPG is a control pulse generator, 14 is an adder, 15 R
EG is a register, and 16 is a data signal output terminal.

In the battery module 1, cells having a nominal EV (volt) are connected in n stages in series, and a total of nEV is obtained. From the connection point of each cell, a conductor for measuring a voltage is drawn out and added to the selection circuit 2. This selection circuit sweeps and selects from the ground 0V to the highest voltage nEV by the control pulse generator 9 and sequentially takes out the output voltages, so that the output voltages are 0V, EV, 2EV, 3EV,
...... Toho is a step wave of the EV step, and A / D of the next step
The voltage is applied to the converter 3 and converted into a digital code representing the voltage. This A / D converter requires 7 bits per EV to measure up to nEV.
Then, it is necessary to add 4 bits to 11 bits.

The output code of the A / D converter 3 is stored in a register 4 and stored for one sweep time. The output code is subtracted from the input code of the register 4 by a subtracter 5. Since the signal to be subtracted by the register 4 is always delayed by one step time from the signal to be subtracted, the output of the subtracter 5 sequentially shows the voltage sign (hereinafter, abbreviated as data) for each cell from the lowest cell to the higher order. ) Will appear.

The output of the subtractor 5 is added to a subtractor 6 at the next stage, where the output code of the register 8 is subtracted. The register 8 is a shift register having an n-stage configuration corresponding to the number of stages of a cell.
The data of each cell transmitted from is recorded in order,
In the subtractor 6, the difference between the previous data from the register 8 and the new data from the subtractor 5 is obtained for each cell. If there is a difference, the adder 7 accumulates the difference in the register 8 as new data. That is,
The adder 7 and the register 8 have an accumulator function, and since the previous data is always recorded by this function, the difference from the new data is obtained from the subtractor 6. As described above, there is no abrupt change in the voltage of each cell in the difference data, so that data representing a large voltage difference is not generated. Therefore, using the above example, +
Only three types of data of 1, 0, and -1 can be sent. If you need to send larger difference data (for example, when charging for the first time),
Until the contents of the register 8 become the same as the data from the subtractor 5, +1 or -1 is repeatedly transmitted.

In this way, since the transmission data is compressed to a fraction, redundant bits for transmission error control can be added, and this operation is performed by the encoder 10. There are many error control methods, each of which has advantages and disadvantages, but a description of these methods is omitted here because it has no bearing on the purpose of the present subject matter.
In the encoder, in addition to the redundant bits, a bit synchronization signal and a frame synchronization signal are added, and transmitted via the transmission line 11 to the receiving side.

On the receiving side, first, clock reproduction and frame signal reproduction are performed by the control pulse generator 13.
The receiving units operate using this. Error control is performed on the received signal in the decoder 2, and redundant bits are removed. The adder 14 and the register 15 constitute an accumulator in the same manner as the transmission unit, and the newly transmitted difference data is added to the previous data stored therein, so that the data signal output terminal 16 Always obtains the latest voltage data.

[0015]

As described above in detail, according to the present invention, even if redundant bits for error control are added by compressing transmission data, voltage data can be stored without reducing the information transmission speed. Can be transmitted. In addition, since all of these sign operations can be performed by a microprocessor, a small-sized voltage data transmission circuit having a simple structure can be configured.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram for explaining the principle and embodiments of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Battery module 2 Sweep type selection circuit 3 Analog to digital converter 4 Register 5 Subtractor 6 Subtractor 7 Adder 8 Register 9 Control pulse generator 10 Encoder 11 Transmission line 12 Decoder 13 Control pulse generator 14 Adder 15 Register 16 data signal output terminal

Claims (1)

[Claims] The transmitting unit subtracts a previous voltage data code stored in an accumulator from a voltage data code sampled and taken out, transmits the difference, and stores the difference in an accumulator. The contents of the accumulator are updated to the latest data code by adding to the voltage data code. In the receiving unit, an accumulator having the same configuration as that of the transmitting unit is provided, and the latest data code is obtained by adding the transmitted differential data to the previous voltage data code stored in the accumulator, and the contents of the accumulator are updated. By having the means of updating to the latest data code,
A battery voltage data transmission system characterized in that transmission data is configured to be able to be transmitted after being compressed.