JPS6231385B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a failure detection circuit, and more particularly to a failure detection apparatus in a memory device used for digital transmission of television signals.

2. Description of the Related Art There are frame encoding devices, still image transmission devices, and the like that digitally transmit television signals in broadcasting or video conferences. However, all of these devices require a frame memory device for storing digital signals for one screen.
Various types of failures in such television signal transmission directly lead to deterioration of service, so it is necessary to create a configuration in which failures are as unlikely to occur as possible and a configuration in which failures can be quickly discovered and repaired.

From this point of view, it is important that the above memory device also satisfy these requirements. One method for this purpose is to add one bit of parity code to the input/output data to the memory device, and detect a device failure by a parity check. Although this method can be realized by adding an extremely simple circuit and can determine equipment failure, it does not allow determining the location of the failure, which increases repair time, and it requires switching the failed equipment to a spare equipment. The disadvantages include that the service is interrupted for a long time because it requires manual intervention in some cases.

Yet another method is to convert the memory device input/output data into error correction codes. In this case, errors in the output data due to the failure are corrected, so it is possible to make it appear that there is no failure at all from the outside, but the error correction encoder and decoder are circuit-complex, and the equipment In terms of size and cost, it was not a good idea to apply it to interframe coding devices, still image transmission devices, etc.

An object of the present invention is to provide a memory device that detects a failure in the memory device, determines the location of the failure, and automatically removes the failure from the system by adding a simple circuit in order to eliminate the above-mentioned conventional drawbacks. The object of the present invention is to provide a failure detection device.

According to the present invention, the first selection circuit selects the i-th bit (i is 1...n) of the n-bit parallel input data and outputs it as a parity code; an (n+1)-bit memory device that stores a first parity code of A second selection circuit that outputs the second parity code as the second parity code compares and collates the first parity code read from the memory device with the second parity code selected by the second selection circuit. an exclusive OR circuit that outputs a mismatch signal when the two codes do not match; and an exclusive OR circuit that determines that the i-th bit has failed when the mismatch signal occurs only in the i-th bit;
an error determination circuit that determines that a failure or error is common to each bit of the memory device when a mismatch signal occurs successively between the th and (i+1)th bit; and a bit selected by the first and second selection circuits. a counting circuit that switches the i-th bit at a predetermined cycle and controls the i-th bit to be fixedly selected and output when the determining circuit determines that the i-th bit has failed; There is obtained a failure detection device characterized in that it comprises an error correction circuit which corrects the i-th bit in accordance with the mismatch signal when it is determined that the i-th bit has failed.

Next, a failure detection circuit according to the present invention will be explained with reference to the drawings. In the drawing, 1 is (n+
1) A memory device (n is an integer) that stores bits. 2 is a first selection circuit that selects the i-th bit (i = 1, 2, 3, ..., n) of n-bit parallel data and outputs it as the first parity code; This is a second selection circuit that selects the i-th bit of the bit-parallel output data and outputs it as a second parity code. 4 is an error correction circuit; 5 is a circuit for detecting a mismatch between the first parity code read from the memory device via the signal line 1a and the second parity code output from the second selection circuit 3 via the signal line 3a; This is an exclusive OR circuit for detection. Reference numeral 6 denotes an error determination circuit connected to the output terminal of the exclusive OR circuit via a signal line 5a. 7
is a counter connected to the error determination circuit 6 via the signal line 6a, and connected to the first selection circuit 2, the second selection circuit 3, and the error correction circuit 4 via the signal line 7a. 8a, 8b and 8c are data buses, respectively.

Next, the operation of the failure detection device with the above configuration is calculated by setting n to 4.
This will be explained with reference to FIG. entered 4
The bit-parallel data is applied to the memory device 1 and the first selection circuit 2 through the data bus 8a. The first selection circuit 2 selects the i-th bit in response to the signal designated by the counter 7 (FIG. 2a), and sends the selected i-th bit to the memory device through the signal line 2a. 1 (Figure 2b). Here, each bit among the n bits is selected consecutively. Therefore, Fig. 2 e, which will be described later.
As shown in , multiple comparison outputs are output.

The memory device 1 stores the above 4-bit input data and the first
The parity code input from the selection circuit 2 is stored, and the read 4-bit data is output to the error correction circuit 4 and the second selection circuit 3. The second selection circuit 3 selects the i-th bit in response to the designation signal of the counter 7 and outputs it to one input terminal of the exclusive OR circuit 5. On the other hand, the parity code (FIG. 2c) read from the memory device 1 is applied to the other input terminal of the exclusive OR circuit.

The exclusive OR circuit 5 outputs "0" when the same signal is applied to the two input terminals, and outputs "1" when different signals are applied (FIG. 2e). The output of exclusive OR circuit 5 is applied to error correction circuit 4 and error determination circuit 6 through signal line 5a. The error determination circuit 5 determines the location of the failure, and determines the error signal sent from the exclusive OR circuit 5 in the determination interval shown in FIG. 1st (1st
+i), it is determined that the i-th bit is faulty (FIG. 2f) and a signal (INH) (FIG. 2g) is output to stop the counting circuit 7. At the same time, this signal (INH) is also sent to the error correction circuit 4. On the other hand, when the above error signal occurs consecutively, such as in the i-th bit and the (i+1)-th bit, it is determined that the part common to each bit of the memory device 1 or the parity code is defective, At this time, the signal (INH) is not output. Note that the reason why a two-bit consecutive error is considered a common part error is that the probability that two bits will be erroneous consecutively is much lower than the probability that one bit will be erroneous.

The counting circuit 7 is a circuit for selecting bits to be tested, and sequentially counts from the first bit to the nth bit in accordance with a pulse signal input having a period for testing each bit. The output signal of this counting circuit 7 is
The first and second selection circuits 2 through the signal line 7a
and 3 to the error correction circuit 4, which selects the check bit. Further, when the error determination circuit 6 determines that the i-th bit among the n bits is faulty and a signal (INH) is output to the counting circuit 7, the counting circuit 7 stops counting and Maintains the state of selecting the th data.

On the other hand, while the error correction circuit 4 is receiving the signal (INH) from the error determination circuit 5, the exclusive OR circuit 4 inputs the i-th bit selected by the signal sent from the counting circuit 7. The bit is corrected by inverting the bit according to the output of the bit.

Therefore, the fault detection circuit as described above can detect a 1-bit error in the memory device 1 with an extremely simple configuration, determine the location of the fault, and automatically correct the error. I can do it.

As explained above, the present invention detects a failure in a memory device by inspecting each bit of parallel input/output data, and determines the location of the failure, thereby automatically detecting a 1-bit failure. It becomes possible to correct it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a failure detection device according to the present invention, and FIGS. 2a to 2g are time charts for explaining its operation. DESCRIPTION OF SYMBOLS 1...Memory device for storing (n+1) bit parallel data, 2...First selection circuit, 3...Second selection circuit, 4...Error correction circuit, 5...Exclusive OR circuit, 6...Error determination circuit, 7... Counting circuit, 8a, 8
b, 8c...data bus.

Claims (1)

[Claims] 1. A first selection circuit that selects the i-th bit (i is 1...n) of the n-bit parallel input data and outputs it as a parity code; bit number 1
an (n+1)-bit memory device that stores a parity code of A second selection circuit that outputs the code as a code compares and collates the first parity code read from the memory device and the second parity code selected by the second selection circuit to determine whether these two codes are the same. an exclusive OR circuit that outputs a mismatch signal when there is a mismatch; and when the mismatch signal occurs only in the i-th bit, it is determined that the i-th bit is faulty, and the an error determination circuit that determines that a failure or error is common to each bit of the memory device when a mismatch signal occurs continuously; and switching bits selected by the first and second selection circuits at a predetermined cycle; a counting circuit that controls to fixedly select and output the i-th bit when the determination circuit determines that the i-th bit is faulty; and an error correction circuit for correcting the i-th bit in accordance with the mismatch signal.