JPS59200342A - Microprogram controller - Google Patents

Abstract

PURPOSE:To reduce the capacity of a control capacity by storing the microinstruction words the same in microinstruction basic part and different in constant field into the same address. CONSTITUTION:The microinstruction words the same in microinstruction basic part and different in constant field are stored into the same address of a control memory 1. A mode FF4 holds a mode which designates one of plural field pairs that is validated in terms of the microinstruction word read out of the memory 1. Thus switches 5 and 6 are switched with said designated mode, and one of plural field pairs is selected for the microinstruction word read out of the memory 1.

Description

[Detailed description of the invention] The present invention relates to a microprogram controller.

As is well known, a microprogram control device stores a microprogram corresponding to each machine language instruction of a software program in a control memory in advance, and reads this control memory in response to the progress of the software program to control each machine. It executes microprograms corresponding to word commands.

Microinstructions allow detailed control of hardware and enable functions that could not previously be achieved with software, so attempts are being made to create and use microprograms tailored to specific purposes. Initial settings and configuration control of information processing systems.

An example of this is unit 7 armware/system control 7 armware for testing, virtual machine implementation, etc.

On the other hand, the microinstruction word for writing a microprogram consists of the microinstruction basic part, which consists of a part that specifies the 7-step control of the microprogram and a part that defines the microinstruction function, and the next part of the microinstruction that is currently being executed. It consists of a next address field for specifying the microinstruction word to be executed, and a field for describing constants or detailed functions of the microinstruction. Outline functions (described in microinstruction base)
There are multiple series of processes that have the same repertoire but different constants or detailed function specifications and microinstruction word processing orders. Conventional microprogram controllers of this type have one next address field, one constant A control memory is provided for storing a microprogram written in a microinstruction word consisting of a field and a microinstruction basic part, and the next address field and constant field in the microinstruction word read from the control memory are used to write the microinstruction basic part. The microinstructions specified by the unit are executed sequentially.

In such a conventional configuration, even if there are a plurality of similar processes with the same basic microinstruction part and different constants as in the above-mentioned system control firmware, separate microinstructions are stored in different address groups of the control memory. Because a group of instruction words is provided and each must be processed by a separate processing routine, the control memory becomes large in capacity, and the time required to decode the address becomes longer, extending cycle time and reducing reliability. shi that decreased
This has the disadvantage of increasing the cost of the device.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a microprogram control device capable of reducing the amount of control memory. Each device of the present invention specifies a microinstruction word to be executed next to the currently executing microinstruction word. a control memory for storing a microprogram written in a microinstruction word consisting of a plurality of field sets including a next address field and a constant or a field for describing details of the microinstruction operation, and a microinstruction basic part; mode holding means for holding a mode that specifies which of the plurality of field sets is to be enabled for the microinstruction word read from the control memory; selection means for selecting one set of the plurality of field sets of the microinstruction word according to the mode, and a microinstruction execution order that differs by the number of the field sets for each of the same microinstruction basic part; The feature is that it is executed with .

Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, this embodiment includes a control memory 1, a microinstruction register 2, and a microinstruction address register (
This microprogram control device is composed of a mode clip 70 (4), two switchers 5 and 6, an instruction decoder 7, and an instruction register 8.

The control memory 1 includes a microinstruction basic unit MI, a first constant field CNT1, a second address field NA2, and a second constant field CNT, as shown in FIG.
2 and a secondary address field NA2. First constant field cNT1. =The primary address field NA1, the second constant field CNT2, and the secondary address field N person 2 are as follows: the first constant CNTl, the primary address I'JAL, the second constant CNT2, and the secondary address NA2. During the initial operation of the seven stems including the microprogram control device abbreviated as 0, the mode flip 70 knob 4 is set by an external initialization signal INT so as to output the mode signal M at logic 101. From the address of the control memory 1 that is initially set in the address register 3, the micro instruction word is read out, and the micro instruction basic part MI, the first
The constant 11cNTI and the second constant CNT2 are input to the microinstruction register 2, and the first address NAI and the second address NA2 are input to the switch 6, respectively.

The switch 5 selects logic 10 from among the first constant CNT1 and the second constant CNT2 held by the microinstruction register 2.
In response to the mode signal M being set to 1, the first constant CN
Select T1. The first constant CNTl is output to the microinstruction execution unit (not shown) together with the microinstruction basic unit MI, and is used to specify register numbers and set registers in accordance with the microinstruction function specified in the microinstruction basic unit MI. value.

Used to specify bits to be manipulated in registers.

The switch 6 selects the primary address NAI and the secondary address N.
A primary address NA11r is selected from A2 in response to the mode signal M which is at logic 10l and is input to the address register 3.

The address register 3 supplies this primary address NAI to the control memory 1 and reads out the microinstruction word from that address again.

Mode 7 lip 70 knob 4 sets mode signal M to logic 10g
As long as it is set to output, as mentioned above,
While selecting the first constant CNT1 and the first address N person 1, microinstructions are read out from the control memory 1 one after another, and the microinstructions are executed in the microinstruction execution section. In such a first processing mode, a microinstruction step is executed such that the mode clip 70 knob 4 switches the mode signal M to logic 111 and outputs it, or the processing in the first processing mode is performed. In order to execute the next software instruction set in the instruction register 8, the instruction decoder 7 sets the microprogram start address for executing the software instruction in the address register 3, and mode FF4 is set to the instruction register 8. When set to logic 111 by the decoder 7, the switches 5 and 6 each have a first constant CNT.
1 and the primary address NAI, the second constant CNT
2 and the secondary address NA2 are selected.

The functions of the second constant CNT2 and the second address NA2 are as follows:
The first constant CNT1 and the first address NA described above, respectively.
The function is similar to that of I. In the second processing mode defined by the second constant CNT2 and the second address NA2, a microinstruction step is executed in which the mode clip-flop 4 switches the mode signal M to logic 101 and outputs it, or After the processing in the second processing mode is completed, in order to execute the next software instruction set in the instruction register 8, the instruction decoder 7 sets the microprogram start address for executing the software instruction in the address register 3. When the mode FF4 is set to logic I01 by the instruction decoder 7, the switches 5 and 6 are set to select the first constant CNTl and the primary address NAI again, respectively. Return to processing mode.

FIG. 3 shows the first processing order in the first processing mode and the second processing mode in which the microinstruction basic parts M'I are the same and the constants used by the microinstruction basic parts are different. The second processing order in the processing mode of FIG. address l'-0
, 2, 3-, 4°5.6" and "7", it can be seen that the microinstruction basic part is used in the first processing order and the second processing order. .

In this embodiment, there are two sets of constants and next addresses, but the present invention is not limited to this, and a plurality of mode 7 lip 70 tabs 4 are provided to send a plurality of mode signals M. If this is allowed to occur, embodiments for micro-instruction words having three or more sets of a constant field and a next address field can be easily implemented.

According to the present invention, by adopting the above configuration, microinstruction words having the same basic microinstruction part and different constant fields are stored at the same address in the control memory, and the constant field and the next address field are stored at the same address in the control memory. Because it can be used in as many different processing cucuns as the number of pairs,
Control memory capacity can be reduced.

[Brief explanation of drawings]

FIG. 1 shows one embodiment of the present invention, and FIGS. 2 and 3 are diagrams for explaining this embodiment. 1... Control memory, 2... Micro instruction register, 3... Micro instruction address register, 4... Mode clip flop, 5, 6...
...Switcher, 7...Instruction decoder, 8.
...Instruction register, INT...Initialization signal, M...Mode signal, MI...
...Microinstruction basic part, CNTl...First constant field, CNT2...Second number field), NA1...First address field,
NA2...Second address field, 5EQ
1,8EQ2...Processing order. 1 F2 Ko? ]; fy2111 years old] 5 -. 3 ri 46
ri ri 5 ri 75-6θ 3rd figure

Claims (1)

[Claims] Each includes a next address field for specifying a microinstruction word to be executed next to the microinstruction word currently being executed, and a field for describing details of a constant or operation of the microinstruction. a control memory that stores a microprogram written in a microinstruction word consisting of a plurality of field sets and a basic microinstruction part; mode holding means for holding a mode specifying whether to enable a set; and selection for selecting one set of the plurality of field sets of the microinstruction word read from the control memory according to the mode. A microprogram control device characterized in that the same microinstruction basic units are executed in different microinstruction execution orders equal to the number of field sets.