JPS59198600A - Data processing system - Google Patents

Abstract

PURPOSE:To simplify the change/replacement operation of information stored in an ROM and also to improve reliability by adding a memory peripheral circuit having an automatic generation function of parity bit so as to form a memory chip for parity bit data formed conventionally by an ROM in the form of an RAM. CONSTITUTION:In the initial state just after application of power, a parity data is not yet stored in an RAM9 for parity bit. Then, even if a CPU1 reads the stored content of an ROM2 for program data, a parity effective/ineffective designating circuit 13 is made invalid so as to conduct the parity error processing. A parity bit forming circuit 10 forms a parity bit data based on the received information and stores it to the first address of the RAM9 for the parity bit. While advancing sequentially the address of the ROM2 for program data and the RAM9 for parity bit, the parity bit is produced over the entire area of the ROM2 for program data, the data is stored in the RAM9, the parity effective/ ineffective designating circuit 13 is switched so as to attain effective parity check function.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a data processing system capable of creating and storing parity bits (parity data) of programs or data stored in a read-only memory.

Generally, in this type of data processing system, it is desirable that parity data can be easily changed by changing programs or data, and that the reliability is high.

[Prior art and its problems]

In microprocessor application systems that have memory units such as ROM (read only memory) and RAM (random access memory) that store programs or data, ROM is mainly used for storing programs.
In order to ensure the reliability of the stored program or data, a parity bit is added to the stored program or data, and a dedicated memory is provided to store the parity bit. There are many things.

FIG. 1 is a block diagram showing a conventional example of a parity data storage system. In the figure, 1 is a central processing unit (CPU) such as a microprocessor, 2 is a ROM that stores programs or data (hereinafter also referred to as programs, etc.), and 3 is a parity bit (parity data) corresponding to the storage contents of ROM2. ), 4 is a parity check circuit, 5 is a data bus, 6 is an address bus,
7 is a parity data line, and 8 is a parity error information line. That is, a ROM 2 for storing programs and the like and another ROM 3 for storing parity bits corresponding to the stored contents of the ROM 2 are provided, and these ROMs 2.3 constitute a storage system.

In this case, the jOROM 3 is created by creating a parity bit using the CPU from a program stored in the ROM 2, outputting it to a paper tape, etc., and then transferring the contents of the tape.

Therefore, the RO
When a predetermined address of M2.3 is specified, the contents of ROM2 are given to the CPUI and parity check circuit 4 via data bus 5, while the contents of ROM2 are sent from ROM3 to
The parity bit corresponding to the content of is connected to parity data line 7.
The check circuit 4 creates a parity bit corresponding to the information provided from the ROM 2 and compares it with the parity bit provided via the line 7. ROM
You can check the contents of 2. Therefore, when a parity error occurs in the data on the data bus 5 due to a defect in the memory or the bus, the parity check circuit 4 detects this and outputs parity error information to the parity error information line 8. In such a case, RoM2,3
are usually mounted on printed circuit boards, etc. via ROM sockets or connectors to facilitate replacement in consideration of changes in memory contents, etc., which increases the number of sockets or connectors used and reduces memory reliability. The drawbacks are that the performance is reduced and the space occupied increases. Furthermore, if it becomes necessary to change the content, order, etc. of a program, it is necessary to change ROM 3 at the same time as changing ROM 2, which has the disadvantage that the changing and replacement operations are complicated.

[Purpose of the invention]

This invention was made to eliminate such drawbacks, and R
An object of the present invention is to provide a data processing system that can simplify the operation of changing and exchanging information stored in an OM, and improve its reliability.

[Key points of the invention]

The key point is to provide a parity data creation circuit that creates parity data corresponding to a program etc. stored in the ROM, and a RAM that stores this parity data in correspondence with each program instruction word. When the power is turned on, a program etc. already stored in the ROM is read out, parity data corresponding to this is created, and this is stored in the RAM.
ROMt for parity data is unnecessary.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the invention. In the figure, 9 is a RAM for storing parity bits;
0 is a parity bit generating circuit for creating a parity bit f), 11 is a parity error line, '12 is an address decoder, 13 is a parity valid/invalid designation circuit, 14 is a decoder signal line, and the other parts are the same as in FIG. That is, the address information output from the CPUI to the address bus 6 is applied to the address terminals of the ROM 2 and the parity bit RAM 9, as well as to the address decoder 12, so the decoder 12 uses the decoder signal line based on the address information. 14, the parity valid/invalid designation circuit 13 is selected. This parity valid/invalid designation circuit 13 is connected to the parity error line 11.
This determines whether to enable or disable the parity error information provided via the RAM.
At power-on, when the parity bit is stored in 9, it is designated as invalid. Further, the data bus 5 is connected to the data terminal of the ROM 2 and the respective input terminals of the parity bit creation circuit 10 and the parity check circuit 4, and the parity bit created by the parity bit creation circuit 10 is The data is supplied to the RAM 9 via the data a7, and is also supplied from the RAM 9 to the check circuit 4.

In the above configuration, the present invention automatically creates parity data corresponding to the storage contents of the program/data ROM 2 when the power is turned on, and stores the parity data in the parity bit RAM 9. This eliminates the need to create a ROM for parity bits as shown in the figure, and the detailed procedure for the process is as follows.

1) In the initial state immediately after power is turned on, parity data is not yet stored in the parity bit RAM 9. Therefore, the parity valid/invalid designation circuit 13 is configured so that parity error processing cannot be performed even if the cPUl reads the stored contents of the program/data ROM 2.
Disable.

2) The CPU reads the first information stored in the ROM 2 for one program and data.

3) The CPUI sends the information read from the ROM 2 to the parity bit creation circuit 10.

4) The parity pit creation circuit 10 creates parity bit data based on the received information and stores it in the first address of the parity bit RAM 9.

5) By repeating the processes of 0 to 4 above while sequentially incrementing the address of RAM 9 for program data, parity is created over the entire area of ROM 2 for program data. A bit is generated and stored in RAM 9.

6] When the above processes 1) to 5) are completed, the parity valid/invalid designation circuit 13 is switched to valid, so that the parity check function is enabled for the output data of the program session data ROM 2 from then on.

Note that if a parity error occurs in the data due to deterioration of stored information or a defective bus of an element,
If the parity valid/invalid designation circuit 13 is valid, it outputs parity error information through the parity error information line 8, but if it is invalid, no parity error information is output.

〔Effect of the invention〕

As described above, by adding a memory peripheral circuit with an automatic parity bit generation function, the memory chip for parity bit data, which was conventionally formed in ROM, can be
It becomes possible to use AM, and the following effects are expected.

b) There is no need for the IC socket or connector of the ROM for storing the parity bit, that is, the RA for the parity bit
Since M does not require replacement, it can be mounted directly on the board (direct mounting).
Therefore, its reliability is improved, and the space it occupies is also reduced.

Mouth) There is no need to create a ROM for storing Haritibit!
l) Since RAM is generally cheaper than ROM, costs can be reduced.

Note that the present invention can be widely applied to systems that require parity bits or data of information stored in a ROM, or systems in general that require a memory to store such data.

[Brief explanation of the drawing]

The first tooth is a block diagram showing a conventional example of a parity data storage system, and FIG. 2 is a block diagram showing an embodiment of the present invention. Description of symbols 1... Central processing unit (CPU), 2... ROM for storing programs, 3... ROM for storing parity data,
4... Parity check circuit, 5... Data bus,
6... Address bus, 7... Parity data line, 8
... Parity error information line, 9... RAM'M for parity data. 10... Parity data creation circuit, 11... Parity data line, 12... Address recorder, 13...
Parity valid/invalid designation circuit, 14... decoder signal line. Representative Patent Attorney Akio Namiki Representative Patent Attorney Kiyoshi Matsuzaki

Claims (1)

[Claims] 1) - A central processing unit that executes predetermined processing, a read-only memory (ROM) that stores predetermined information, and the RO
A parity data creation circuit that creates parity data corresponding to each piece of information stored in M, and a random access memory IJ (RAM) that stores the parity data.
and the central processing unit is configured to control the R when the power is turned on.
A data processing system characterized in that by sequentially reading each piece of information stored in an OM and providing it to the parity data creation circuit, the parity data obtained through the creation circuit is sequentially stored in the RAM. 2) A central processing unit that executes predetermined processing, a read-only memory (ROM) that stores predetermined information, and the ROM
a parity data creation circuit that creates parity data corresponding to each piece of information stored in the ROM; a random access memory IJ (RAM) that stores the parity data; The central processing unit is equipped with a parity check circuit that performs a parity check based on the parity check circuit, and a valid/invalid designation circuit that designates whether the output of the parity check circuit is valid or invalid. By reading the parity data and providing it to the parity data generation circuit, the parity data obtained through the generation circuit is
A data processing system characterized in that the data are sequentially stored in predetermined locations of an AM, and the output from the parity check circuit is made invalid via the valid/invalid designation circuit at least when such an operation is being executed.