JPS59197917A - Device for controlling process input-output - Google Patents

Abstract

PURPOSE:To automatically repeat data input and output into and from an I/O module belonging to a CPU under the operation mode set in the CPU in advance and reduce the burden of the CPU, by performing the data communication between the CPU and a serial I/O controller through an I/O data port memory. CONSTITUTION:An I/O 2-port memory 5 is connected to the CPU1 of an input- output controlling device through an address bus 21, data bus 22, and control signal line 24. Moreover, a serial I/O controller 3 is connected to the CPU1 through a control signal line 23 and, at the same time, the memory 5 and controller 3 are connected with each other by means of an address bus 25, data bus 26, and control signal line 27. In addition to the above, plural I/O modules 4a- 4n are connected to the controller 3. Then the data communication between the CPU1 and controller 3 is performed through the memory 5 and data input and output into and from the modules 4a-4n belonging to the CPU1 are automatically repeated under the operation mode set in the CPU1. Thus the burden of the CPU1 is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for controlling the process of Sibrand using a computer, by connecting each input/output (hereinafter referred to as "input/output") module and central processing unit (hereinafter referred to as "CPU"). This relates to a control device for inputting and outputting process data (status signals such as ON/OFF of external contacts, command signals such as driving relays, specifying flow rate, pressure, etc.).

Conventionally, there has been a device of this type as shown in FIG.

In the figure, (1) is the CPU, and 121 is the CPU path.
The PU bus consists of an address bus (2υ), a data bus (22), and a control signal line (23). (3) is a serial Ilo core controller, (4al (4b), -(4
n) is each I10 module.The operation will be explained next. For example, when the CPU fil attempts to input data from the ■n module (4a), the data is sent to the ■n module (4a) via the CPU bus +21.
4a) and the input command are given to the serial I10 controller (3). This input command is serial I.
The 10 controller (3) sends an input command to the I10 module (4a). Upon receiving the input command, the module (4a) takes in all the process information (i.e. status signal) and converts it into a signal in the form of a bit series. Serial I
10 controller (3).

After receiving the transmitted process information, the Series I10 controller (3) sends it to the CPU (1) via the CPU'U bus +21, and when this sending operation is completed, the CPU [11] Upon receiving this notification that the input operation has been completed, the CPU (11) moves on to the next process.

If the next process after CPU (11) is to send output data to the I10 module (4), CPU (
11 is the I10 module (
4b) selection signal and output command, and the output data to be output by this output command are sent to the serial I/'0 controller (
3) Enter. The serial I10 controller (3) sends an output command and subsequently output data to the f10 module (4b). When the I10 module (4) receives an output command and output data, it executes all control operations instructed by the output data.The serial I10 controller (3) executes the CPU +1 when the output operation is completed.
1 is notified of the completion of the output operation, and upon receiving this, the CPU fil proceeds to the next process.

Since the conventional device is configured as described above, the CPU
tll U Each time input/output is performed for one I/CTh module, input/output commands must be set in the serial I10 controller (3), which places a large burden on the CPU (11) for process input/output processing. However, input/output operations are often performed repeatedly in a predetermined order among multiple I10 modules controlled by one serial I10 controller (3). is a serial I10 controller (31 can repeatedly execute input/output control for each I10 module in accordance with the predetermined order described above), and a CPU (31 does not need to issue commands each time; input/output data can be sent at one time. The memory device for storing data may be provided between the i7 CPU tll and the serial I10 controller (3).

This invention was made in view of the above facts.
Data is exchanged between the CPU and the serial I10 controller via the I10 data port memory, which can be accessed from both the CPU and the serial I10 controller. (The purpose is to reduce the burden on the CPU for process input/output processing by repeating bit-serial data 9 transfers.) Hereinafter, embodiments of the present invention will be explained with reference to figures.Second
The figure is a block diagram showing an embodiment of the present invention, in which the same reference numerals as in Fig. 1 indicate the same - or corresponding parts, (5) is the data 2-port memory, and (24) + is from the CPU (1). I1
0 data 2 boat memo January 5) control signal line to (25
), (26), and (27) are the address bus, data bus, and control signal lines between the serial controller (31 and the I10 data 2-port memory (5). Data can also be written and read from both the CPU tll and the serial controller (31).

Next, the operation will be explained. In the operation mode set in the serial I10 controller in advance from the CPU fil, for example, input operation from the I10 module (4a) (hereinafter abbreviated as operation A) → output operation to the I10 module (4b) (hereinafter abbreviated as operation B) ) → Input operation from the envy module (4c) (hereinafter abbreviated as operation C) 9 → Output operation to the I10 module (4n) (hereinafter abbreviated as operation N) → Predetermined time (this time may be O) )'s operation suspension (hereinafter abbreviated as operation P) is A-
+B-+C-+N+P-+A → B → is set to be executed repeatedly 9, and the I10 data 2 port memory has the address of the location where data corresponding to each I10 module should be stored. .

The serial I10 controller (3) first sends an input command to the I10 module (4a). Serial I1
The operation of each I10 module in response to instructions from the 0 controller is the same as the conventional one explained with reference to FIG.
The serial I10 controller (3) that received the data from the I10 data 2-port memory (5)
After writing this data to the address location corresponding to a), immediately proceed to the next process. The output command and output data are sent to the serial I1.The output completion notification that the I/'Q module (4b) has completed the control specified by this output data is sent from the serial I1
When the 0 controller (3) is reached, the next process of the serial I10 controller (3) is the operation CK').
After the operation N and the operation P, the operation A is executed again, and these repetitions are performed until a stop command is input from the CPU (1) to the serial I10 controller (31).

Therefore, each L module (4a) to (4n) of the CPU (11 is I10 data 2 port memo January 5 as necessary)
), the load on the CPU (11) is greatly reduced.The number of I10 modules and the input/output mode can be arbitrarily set. , (2) The data 2-port memory (5) may be any memory having a capacity corresponding to the number of L modules.

As described above, according to the present invention, data exchange between the CPU and the serial controller 2 is carried out via the I10 data 2-port memory, and the serial I10 controller transfers all the data belonging to it according to the operation mode set by the CPU in advance. Since the data input/output control for the I10 module is configured to be automatically repeated, it is possible to provide a process input/output control device in which the load on the CPU for process input/output processing is small.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional device, and FIG. 2 is a block diagram showing an embodiment of the present invention. (1)...CPU, +21...CPU bus, (3)
...Serial L controller, (4a) to (4
n)...I10 module each, (5)...I
10 data 2-port memory Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2 Showa Year Month Day 2 Name of the invention Process input/output control device 3 Relationship to the person making the amendment Patent applicant Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Hitoshi Katayama 4, Agent address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo (
1) The scope of claims in the specification shall be amended as shown in the attached sheet. (2) In the 11th line of page 3 of the specification, the phrase ``bit serial'' is corrected to ``bit serial.'' (31st Letter, Page 3, Lines 14 to 16 “After receiving it, it is sent to the CPU [11] via CPU path (2)...
・Correct the phrase "to the CPU tl+ upon completion" to "to the CPU (11) after receiving". (41st Letter, page 3, line 17, "Proceed to the next process.")
Correct the statement to read "Read the process information and move on to the next process." (5) On page 5, line 13 of the same book, the phrase ``bit serial'' is corrected to read ``bit serial.'' 7. List of Attached Documents (1) Revised Claims 1. Reverse printing Paper 2. Claims The serial input/output controller can also be accessed from the central processing unit, and the above d11 serial input/output controller can be accessed from the central processing unit. All data to be input/output between the central processing unit and the plurality of input/output modules via the input/output data 2-port memory which can be stored in address locations distinguished for each input/output module of the plurality of input/output modules. Then, in the serial input/output controller, according to the operation mode set in advance by the central processing unit, the data read from the input/output data 2 port memory is sent to the corresponding input/output module in a bit serial format along with a command. means for transmitting the input command as a signal, transmits all the input commands to the corresponding input/output module, receives the data transmitted as a bit serial type signal from the input/output module according to the input command, and transmits the data to the input/output data port 2. means for writing to a corresponding address location of the memory; and in the central processing unit, performing necessary writing to the input/output data 2 boat memory;
A process input/output control device comprising means for performing necessary reading from a boat memory.

Claims (1)

[Claims] Data that can be accessed from both the central processing unit and the serial input/output controller, and that is to be input/output between the central processing unit and a plurality of input/output modules via the 71 Noal input/output controller. The input/output data 2-port memo IJ, which can store the input/output data in address positions distinguished for each input/output module of the plurality of input/output modules, and the serial input/output controller, the input/output data set in advance by the central processing unit. According to the operation mode, the data read from the input/output take 2 port memory is transmitted to the corresponding input/output module together with an output command as a bit serial type signal, all input commands are transmitted to the corresponding input/output module, and this input command is transmitted to the corresponding input/output module. means for receiving data transmitted as a bit serial type signal from the input/output module and writing it into a corresponding address position of the input/output data 2 port memory; and in the central processing unit, the input/output data 2 port Write the necessary data to the memory and write the input/output data 2 above.
A process input/output control device comprising means for performing necessary reading from a port memory.