JPH0254360A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the availability of a semiconductor integrated circuit together with the miniaturization and to shorten the bus wiring by attaining the common application of a local CPU and a ROM and at the same time adding plural channels to a serial communication circuit and adding the capacity equal to the number of channels to a dual port memory. CONSTITUTION:In case a 1st system produces the information to be sent to a 4th system 16, for example, the data on the area allocated to a system 16 in a dual port RAM 31 of a slave 3 or to a dual port RAM 41 of a slave 15 is rewritten. When this writing action is detected by a local CPU 34, the data obtained after an address rewritten and the error check data are sent to the slave 15 via a serial communication circuit 23c and a serial communication channel 14. In case the system 16 produces the information to be sent to the system 1, the serial data is sent to the circuit 23c via a channel 14 and decoded by a slave 3. This decoded data is rewritten into an area allocated to the RAM 41. The same action is carried out also with the transmission/reception performed between the system 1 and the 2nd and 3rd systems 2 and 12 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a slave microconvenience that performs communication between processors in a distributed processing system.

[Conventional technology]

When a dual-port memory is used for data exchange between processors in a distributed processing system, normally the two ports of the dual-port memory are directly connected to the buses of the two systems that transmit data. If a direct bus connection is difficult, a slave microcomputer for data communication is used as shown in FIG.

Figure 4 shows the patent application No. 62-9119 filed by the applicant.
No. 4 and Japanese Patent Application No. 62-91195.

In this figure, 1.2 indicates the first and second
The systems 1 and 2 are connected via a bus 5, a first slave microcomputer 3, a serial communication channel 7 and a second slave microcomputer 4 and a bus 6.

Slave microcomputer (hereinafter referred to as slave)
) 3 (4) is configured as one semiconductor integrated circuit, and has a local central processing unit (CP) that performs internal control.
U) 34 (44), ROM (read-only memory) 35 (45) that stores the control program, Soubo 1-RIV (random read/write memory) 3H41) that stores communication data, and communication with the other party. a serial communication circuit 33 (43) connected to the serial communication channel 7 to perform
, which are interconnected by an internal bus 32 (42). RAM31 (4
The other port of 1) is connected to system 1(2).

In the above device, the first system 1 to the second system 2
The operation of transmitting data to the computer will be explained below. First, the system 1 accesses the dual port RAM 31 via the bus 5 and rewrites the data at a predetermined location. When the local CP port 34 of the slave 3 detects that the data in the dual-port RAM 31 has been rewritten, it serially communicates the address of the rewritten dual-port RAM 31, the rewritten data, and error check data according to a predetermined protocol. Write to circuit 33.

It is then transmitted to the slave 4 via the serial communication channel 7. On the other hand, on the slave 4 side, the CPυ 44 decodes the data received by the serial communication circuit 43 according to a predetermined protocol and writes it into the dual port memory 41.

In this case, writing is to the dual port RAM in slave 3.
31 to the same address.

In this way, the contents of the dual-port RAMs 31 and 41 of the slaves 3 and 4 are always the same, and the systems 1.2 appear to share the same dual-port RAM, allowing smooth data communication.

It goes without saying that the data transfer from the system 2 side to the system 1 side is performed in the opposite manner to that described above.

Figure 5 shows System 1 centered around System 2.3.4 System 2.
12.12.16 and 1:3 communication is schematically shown. 3.4 system 12.16 respectively bus 13
．． 17 to slave 11.15.

On the other hand, the system 1 includes slaves 8 and 9 similar to the slave 3 in addition to the slave 3 for communication with the second system 2, and these slaves 3, 8 and 9 are connected to the first system via a bus 5. ing. Slave 8 and slave 11 are connected through serial communication channel 10, and slave 9 and slave 15 are connected through serial communication channel 14. In such a device, slaves 3 and 4, slaves 8 and 11 are connected as in the case of l:1 communication in FIG.
, the contents of each dual-port RAM of slaves 9 and 15 are always made equal.

[Problem to be solved by the invention]

As shown in FIG. 5, in the process of communicating with a plurality of systems, a slave is required for each system, which increases the number of integrated circuits used and lengthens the bus wiring.

In addition, when the communication frequency is low, there is a problem that the local CPU usage efficiency is poor, and the local CPU of each slave
Although the processing procedure of U is the same, the ROM of each slave
There is waste, such as the need to store them separately.

The present invention has been made to solve these conventional problems.1: In the case of a device that performs communication between multiple systems, the local CPU and ROM are shared to increase their utilization efficiency, and the circuit The purpose of the present invention is to provide a semiconductor integrated circuit that can be miniaturized and shorten bus wiring.

[Means to solve the problem]

In order to achieve the above-mentioned object, the present invention utilizes a local CPU.
, the ROM is shared, a plurality of serial communication circuits are provided, and the dual port memory has a capacity corresponding to the number of channels.

[Effect]

A local CPU controls a plurality of serial communication circuits according to a program in a ROM and communicates with other slaves. The data to be communicated is written into the corresponding area of the dual port memory.

〔Example〕

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor integrated circuit of the present invention will be described in detail below with reference to drawings showing an embodiment for performing 1:3 communication.

FIG. 1 is a block diagram showing the configuration of the circuit of the present invention. The first system 1 is connected via a bus 5 to a slave 3, which is a semiconductor integrated circuit according to the invention, which is connected to slaves 4.11 and 15 via serial communication channels 7.1o and 14, respectively. Each connected slave 4, 11
and 15 are connected to the second system 2, the third system 12 and the fourth system 16 via buses 6.13 and 19, respectively.

Slave 4.11.15 has dual port RAM4 as before.
1. Series communication circuit 43, local CPU 44 and RO
Each has one M45. On the other hand, the slave 3 according to the present invention includes a dual-port RAM 31 with a capacity three times that of the dual-port RAM 41, serial communication circuits 33a, 331) and 33c for three channels, and a local CPIJ3.
4 and ROM35, which are connected to the internal bus 3.
Connected by 2.

The ROM 35 stores programs for processing as detailed below. Figure 2 shows local CP
3 is a flowchart showing a processing procedure regarding transmission and reception of U 34; Local CPU 34 is serial communication circuit 33a
, 33b, 33c to each slave 4.11.1
5, a code requesting all data transmission is transmitted (step #1). Next, check whether the dual port RAM 31 has been rewritten with data from the system 1 side (step #2
), if it has been rewritten, the address, data contents, and data for error checking are sent to the serial communication circuits 33a and 3.
3b or the slaves 4, 11 via the serial communication circuit 33c.
or 15 (Step #3).

The dual port RAM 31 has areas defined corresponding to each of the dual port 1-RAMs 41 of the slaves 4, 11 and 15, and the dual port RAM 41 corresponds to the rewritten area.
The slave device sends the above data. If there is no rewriting, only data for error checking is transmitted (step I4).

Next, check whether the retransmission request necessary flag is set/reset (step #5). The retransmission request necessary flag is a flag that is activated when slave 3 becomes the receiving side and there is an error in the received content, and if it is set, it sends the retransmission request code to the slave in question. Send a message (step flag 116). If this flag has been reset, the process moves to the next step l17. step +1
In step #7, it is checked whether the all data transmission request flag is set/reset, and if it is set, the all data communication request code is transmitted (step #8). The retransmission request necessary flag is a flag that is set and reset for data that is a unit of transmission, and the all data transmission request necessary flag is a flag that is set when retransmission is required for all data. If this flag has been reset, the process moves to step #9.

In step 19, the retransmission request flag is checked and this is confirmed.
/ ), perform retransmission processing (step +
110), the retransmission request flag is set when there is a problem with the data transmitted from the slave 3 and the transmission destination reports this fact. If this flag has been reset, the process moves to step Ill.

Next, check the all data transmission request flag (step 111).
1), if this is sent, send all data (step 112). This all data transmission request flag is sent when there is a request for retransmission of all data transmitted from the slave 3.

If this flag has been reset, the process returns to step #2.

While the above processing is being performed, the local CP
When U34 is interrupted by reception, processing according to the flowchart of FIG. 3 is performed. First, it is checked whether the transmitted code is a retransmission request code (step I21), and if it is this code, the retransmission request existence flag is set (step 1122).
According to the process of 9.1110, the corresponding data will be retransmitted to the corresponding slave. If it is not a retransmission request code, check whether it is a full data transmission request code (
Step 1123), if it is this code, sets the all data transmission request flag (step I24). In this case, all data is transmitted to the slave in accordance with the processing in steps Ill and 112 described above. If the sent code is not a full data transmission request code, it is checked whether it is only data for error checking (step 125), and if it also contains an address and data, it is received at the corresponding address of the dual port RAM 31. Write the data (
Step #26), then move to step +127. If the data is only for error checking, proceed directly to step 127.
Move to.

Next, the entire received data is checked (step 1127), and if there is an error, a flag indicating that a request for sending all data is required is set (step n28). In this case, step 1 mentioned above
7. Requests the corresponding slave to transmit all data through the process of 18.

After the flag is set, or if there are no errors in all the data, the presence or absence of a reception error is checked (step 1129), and if there is an error, a retransmission request necessary flag is set (step +130). In this case, steps 15 and 16 described above
The process requests the corresponding slave to retransmit the data.

Next, specific operations will be explained. When the first system 1 generates information to be transmitted, for example to the fourth system 16, the system 1 transfers the information via the bus 5 to the dual port RA of the slave 3.
System 16 or slave 15 twin baud in M31)
Rewrite the data in the area allocated to RAM41. Local CPIJ 34 is dual port RAM with step +12
31 is detected, the address, the data after rewriting, and the data for error checking are transmitted to the slave 15 via the serial communication channel 14 of the serial communication circuit 23C1 according to a predetermined protocol (step 13). The processing related to reception in the slave 15 is the same as the conventional one.

On the other hand, when information to be transmitted from the fourth system 16 to the first system 1 occurs, for example, the system 16 transmits information to the serial communication circuit 2 via the serial communication channel 14 in a conventional manner.
It sends serial data to 3c.

The slave 3 decodes this data according to a predetermined protocol and sends it to the fourth system 16 or the dual port I of the slave 15. Write to the area allocated to AM41 (step 1126).

The above operation is the second one. The same holds true for transmission and reception between the third system and the first system.

〔Effect of the invention〕

The local CPU 34 in the slave 3 of the present invention described above
Because it performs almost no processing other than during communication, it does not require particularly high processing power, and a one-channel communication system or a roadside system is sufficient. Also this local CPIJ
The capacity of 120M35 to store 34 programs does not require much larger capacity than in the case of l-channel communication. Therefore local CPU 34. R.O.
Not only does the utilization efficiency of M35 increase, but the entire device can also be made smaller compared to the case where three slaves are used as shown in FIG. Accordingly, the bus can be shortened, the load on the CPU of the system 1 bus can be reduced, and circuit design can be facilitated. Furthermore, since only one semiconductor integrated circuit is required, the present invention has excellent effects such as cost reduction.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a distributed processing system using a semiconductor integrated circuit according to the present invention, FIGS. 2 and 3 are flowcharts showing the processing procedure thereof, and FIG. FIG. 5 is a block diagram of a distributed processing system using a conventional semiconductor integrated circuit. 3, 4.11.15...Slave 31...Dual port RAM33a, 33b, 33c...Serial communication circuit 34...Local CPU35...ROM In addition, in the figure, the same reference numerals are the same or equivalent Show parts. Agent Masuo Oiwa

Claims (1)

[Claims] 1. A central processing unit, a dual-port memory whose one port is connected to the central processing unit and the other port is connectable to the outside, and a plurality of dual-port memories that are connected to the central processing unit and communicate with the outside. A semiconductor integrated circuit comprising a channel serial communication circuit and a memory storing a processing program for the central processing unit.