JPS59196661A - Led array driver - Google Patents

Abstract

PURPOSE:To imporve the scanning speed of an LED array by changing over an address counter and a line buffer at data write into those having a different frequency at data read in an LED array driver. CONSTITUTION:When a frame synchronizing signal FSYNC is inputted, a write clock signal WCLK and a line synchronizing signal LSYNC are outputted from a timing control circuit 10, and a picture signal WDATA is inputted to a shift register 3 in synchronizing with those signals. The picture signal WDATA is serial/parallel-converted by a 4-bit shift register 3 and stored in an RAM 13 or an RAM 14 in a line buffer 1 or a line buffer 2 for one line's share. Then, the wirte and read lines are changed over, and counters are changed over into address counters 19,20 for read operating in a clock frequency f2 higher than that at write at the same time. Since the data is read from one RAM of line buffer while it is written in another, so the high speed data processing is attained.

Description

[Detailed description of the invention] Technical field The present invention relates to an LED array driving device.

BACKGROUND OF THE INVENTION LED arrays are commonly used as optical writing heads in printers. Here, when an LED array driving device has a line buffer for two lines and scans each line by alternately writing to and reading from the RAM in the line buffer, conventionally, the clock frequency of the address counter of the RAM is The same frequency is used for writing and reading.

In this case, to increase the scanning speed of the LED array, RA
The time required to read data from M and latch it must be made faster. However, when an LED array is used in an optical write head, the data write speed to the RAM is determined by the data access time of the host connected to the head, and the clock frequency of the convolution and read address counters is the same. Otherwise, the data latch takes a long time and limits the scanning speed of the LED array.

Purpose The present invention was made in view of the above points.
LED that can improve the scanning speed of D array
Aim to obtain after array drive.

composition An embodiment of the present invention will be described based on the drawings.

First, basically, as shown in the block diagram of FIG.
A line buffer 1.2 that stores signals for a line, a latch circuit 5 that latches the read signal of the line buffer 1.2 to flash the LED array 4 according to the stored data, and a latch circuit 5 that flashes the LED array 4. 1-transistor array 6 for lighting the signal of the line buffer 1.2 read out for the purpose, a timing signal generation circuit 7.8 for generating timing signals for each circuit, a clock signal generation circuit 9 for driving each circuit, and timing control. It is composed of a circuit 10. 11 is I10 baud 1-, and 12 is a scanning transistor array. Here, input/output processing is performed in units of 4 bits. In addition, there are two sets of line buffers 1.2, RAM 13.14 (both 2048 bits), and data selector 15.16.1.
7, a write address counter 18, and a read address counter 19.20. Writing and reading data is 2
This is done by alternately using the RAMs 13 and 14. In other words,
One line buffer 1 or 2 is used to read out one line of input image signal data stored in the RAM 13 or 14.

Therefore, the push address counter 18 is given a clock frequency fl, and the read address counter 19 is given a clock frequency fl.
．． 20 is given a clock frequency fl, and is set to f 1 < f 2 . Further, an R/W switching unit 21 is provided which switches between writing and reading based on the signal RA/WB from the timing control I-roll circuit 10.

By the way, as shown in Fig. 2, the LED array 4 has 32 elements per chip arranged in 64 columns to form 2048 pins, and the input data line ID is 32+2+2==
The chip selection line CS consists of 128 bits and 64 bits. Therefore, in order to drive such an ED array 4, since the input/output has a 4-bit configuration as described above, the write data is latched in 128-bit units into the latch circuit 5 in units of 4 bits. , the chip selection line C8 is shown in FIG.
33, then 3.4.34.35, the chips are selected and the LED of each bit is lit. Now, when a printer is constructed using electrophotographic technology using the LED array 4, the light P emitted from the LED forms an image on the photoreceptor, but if the energy required per 1 c is J, then J= It is expressed as P・η0・T・1/S. Here, P is the LED light emission amount (W).

η0 is the optical conduction efficiency, T is the application time to the LED (S)
, S is the exposed area (cJI?). From this equation, the application time T required for exposure is T=J-8/P·η0. In other words, the application time T is determined by the photoreceptor and the LED array optical system. As a result, L E
The time required to drive D is 12 times the image signal data.
It can be considered as the sum of the time required to transfer 8 bits and the application time T. Therefore, if the time required to transfer 128 bits of image signal data is shortened, LE
The writing speed of the D array 4 can be increased, and this is achieved because the clock frequency f2 of the read address counters 19 and 20 is high. On the other hand, when writing the input signal to the RAM of the line buffer, it is sufficient to write the input signal into the RAM while the signal for one line is being written onto the photoreceptor. f1 may be lower than fl.

By the way, in order to specify which chip of the LED array 4 is to be lit, the transistor is generally turned off at a predetermined timing.
Used in N-OFFL/. Here, as mentioned above, 128
When lighting up bits at the same time, even if a current of 40mA flows through one element, a current of 40mAX12B = 5.12A must be switched, and the transistor must be equipped with a large heat sink, etc.
In some cases, it may be necessary to connect a drive circuit to drive with L or the like. In this respect, as shown in Figure 3, L E
A scanning transistor array 12 is connected in parallel to the D array 4, and although the output current of this transistor array 12 is about IA, it can be driven by TTL or the like.
The required output current can be obtained by connecting several in parallel.

Next, FIG. 4 shows a timing chart according to this embodiment. Now, when the frame synchronization signal FSYNC is input, the timing control circuit 10 outputs the write clock signal WCLK and the line synchronization signal LSVNC.
is output, and the image signal WDATA is input to the shift register 3 in synchronization with both signals WCLK and LSYC.

This image signal WDATA is transferred to the 4-pin 1- shift register 3.
Serial-to-parallel conversion is performed by line buffer 1.
Or one line (2048 bits) is stored in the RAM 13 or 14 in the memory. Once this operation is complete,
The write line and the read line are switched, and at the same time, the read address counter 19, 20 operates at a higher clock frequency f2 than during writing. Here, LED array 4
The LED array 4 is turned on in units of 128 bits, but in this embodiment, as shown in FIG. 2, the LED array 4 is divided into two parts each having 1024 bits, so that each part can receive 64 bits of data. Therefore, in order to input 128-bit data, the read address counter 19.20
is composed of two pieces, 0~1023.1024~2047
The address counters 19 and 20 are switched to access each bit in units of 4 bits to 64 bits.

In this way, initially 1~63.1024~1087
The 128-bit data for each device is latched into the latch circuit 5 in units of 4 bits, 0 to 6 at predetermined timing.
3. The 1024-1087 bit LEDs will light up according to the latched data. This is one block of operation, and this type of operation is repeated 16 times (0 to 15).
) is repeated to scan one line of 2048 bits. During this time, RAM1 of the other line buffer 2 or 1
4 or 13, the image signal of the next line is stored in memory.

In this embodiment, the shift register for inputting/outputting data to and from the RAM in the line buffer and for serial/parallel conversion of input data is performed using 4 bits, but this may be performed using 8 bits. If you make 8 pins 1- like this, 128
Bit latch time can be shortened, and one line scanning time can be further shortened.

Effects As described above, the present invention provides a write address counter and a read address counter with different clock frequencies, and switches between the two address counters when writing and reading data to and from the line buffer. Therefore, while writing to the RAM of one line buffer, data is read from the RAM of the other line buffer.
The ED array can be turned on, thereby reducing data throughput and shortening the scanning time of the LED array.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention, and FIG. 1 is a block diagram, FIG. 2 is an arrangement diagram of an LED array, FIG. 3 is an arrangement diagram of a transistor array, and FIG. 4 is a timing chart. 1-2 line buffer, 4... LED array,
18...Writing address counter, 19-20...
Read address counter, f1-f2... Clock frequency procedure correction band (bin) 1. Display of the case Japanese Patent Application No. 58-71032 2, Name of the invention LED array drive device 3, Person making the amendment Relationship to the case Patent applicant address 1-3-6-4 Nakamagome, Ota-ku, Tokyo, Agent: 107 Address 5-9-15 Minami-Aoyama, Minato-ku, Tokyo July 1982
Month 26th (shipment date) 6. Subject to correction

Claims (1)

[Claims] In an LED array driving device that drives an LED array having a plurality of light emitting parts in a time-division manner, a plurality of line buffers each having a write address counter and a successive address counter with different clock frequencies are provided, and the data write and read times are controlled by the LED array drive device. An LED array driving device characterized in that the address counter and the line buffer are sequentially switched at times.