JPS62267168A - Apparatus for transposition processing of matrix data - Google Patents

Abstract

PURPOSE:To easily deal with a high integration, by a transposition processing wherein data are inputted in parallel in N pieces of the first line of a memory means arranged in M-th line/N-th row, while data are outputted in parallel from M pieces in the N-th row and the data is shifted into the direction where a line and a row increase. CONSTITUTION:For examples, M=N=4 is set, input means 321-324 are used to input data to respective four memory means 3111-3114 belonging to a first line in parallel. When data are set, said data are shifted to a line-increasing direction by a line direction shift means 34. At this time, the next data are inputted to the memory means 3111-3114 belonging to the first line. When storing of data has been completed in all of 4X4 memory means 3111-3114, data are read out from the memory means 3114-3144 belonging to fourth row in parallel. In parallel with this operation, the shift of data is performed in every row by a row direction shift means 35. Then, in the same way, the shift of the data in the row direction is successively performed. by this processing, integration becomes easy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a matrix data transposition processing device used in an image forming apparatus using light emitting diodes. The present invention relates to a matrix data transposition processing device for transposing matrix data constituted by N groups of signal sequences according to a certain rule, and supplying the transposed matrix data to, for example, the above-mentioned light emitting diode drive unit.

``Conventional technology'' With the spread of Japanese word processors and computers, opportunities to print out sentences, figures, and various data created by these devices are increasing, and various output devices for this purpose have been developed. It has come to be.

A laser printer is a typical non-impact printer that forms an electrostatic latent image on a photoreceptor. A laser printer scans the surface of a photosensitive drum with a laser beam at high speed, and forms an electrostatic latent image of image data by controlling the on/off of the laser beam. The formed electrostatic latent image is developed by a developing device to create a toner image. The toner image is transferred to the printing paper and fixed.

Laser printers can perform printing operations at high speed. However, an optical system such as a polygon mirror is required for scanning, making the apparatus expensive and large. Another disadvantage is that a sophisticated control circuit is required to correct the optical system.

Therefore, recording apparatuses such as printers have been developed in which scanning of an optical image on a photoreceptor is performed using a light emitting diode (LED).

FIG. 11 shows the basic configuration of a device using this LED. This device includes a photosensitive drum l for forming an electrostatic latent image or a toner image. Around the photosensitive drum 1, a charger 2, an LED array head 3,
A developing device 4, a transfer device 5, a cleaning device 6, etc. are arranged.

The charger 2 is used to uniformly charge the photosensitive drum 1 with positive or negative charges, and is usually called a charge corotron. The LED array head 3 is L E
A large number of LEDs 7 are arranged in a row on the surface facing the photosensitive drum 1, and each LED 7 corresponds to a respective printed dot. A drive circuit (not shown) is arranged in the LED array head 3, and the lighting of each LED 7 is controlled independently by this. ■ Between the ED array head 3 and the surface of the photosensitive drum facing it, a convergent rod lens group (not shown) is arranged parallel to the LED array head 3, and the blinking operation of the LED 7 is controlled line by line. When this is repeated in order corresponding to the image information, the blinking information of the light is supplied to the photosensitive drum 1 one line at a time. At this time, the photosensitive drum 1 is rotating in the direction of the arrow. As a result, the surface of the photosensitive drum 1 is moving in the sub-scanning direction, and the LED array head 3 is moving line by line.
When the drum is driven, an electrostatic latent image is formed on the drum surface using the rusk scan method.

The developing device 4 develops the electrostatic latent image thus formed with toner to create a toner image. The created toner image is transferred onto printing paper 8 by the action of transfer device 5. The transfer device 5 is a corona discharge device like the charger 2, and is usually called a transfer corotron. The printing paper 8 is fed from a paper supply tray (not shown), and after the toner image is transferred, it passes through a fixing section (not shown), where the image is fixed. Printing paper that has been fixed is
Similarly, the paper will be ejected onto a paper ejection tray (not shown).

As can be understood from the above explanation, each LED 7 arranged in the LED array head 3 repeatedly turns on or off on a line-by-line basis depending on the corresponding image information. For this reason, the drive circuit of the LED array head 3 is supplied with a binary image signal line by line to individually control on/off all the LEDs 7 to record white or black dots. Become. If such image signals are supplied pit-serially, as the recording density and recording width (length in the main scanning direction) increase, the time it takes to set them in the drive circuit increases, making it impractical for practical use. It becomes impossible to obtain the recording speed. Therefore, conventional techniques have been used to set bit-serial image signals in a relatively short time.

FIG. 12 is for explaining this.

As shown in the figure, this LED array head 3 is provided with a plurality of (eight in this example) shift registers 1. These shift registers 1 are configured to divide and set the image signal into predetermined amounts and control the driving of the corresponding LEDs.

In this example, the image signal 12 for one line is divided into eight parts each having a fixed amount as shown in the figure, extracted as shown by the arrow 14, and transferred to each shift register 1 individually. When the image signals 12 are transferred in parallel as shown by these eight arrows 14, the image signals 12 are transferred into the shift register 11 in the same arrangement as when they are set in a shift register with a combined length of eight lines. is stored in What's more, the transfer speed is eight times faster than when only one line is used.

In this example, as shown in FIG. 13, the image signals stored in the memory device 15 are picked up in consideration of the arrangement for transferring them to each shift register 11, and are transferred to the shift register 16 that can store 8-bit image signals. Store it once. Then, the stored image signals are output in parallel, and
The process of transferring data to the eight shift registers 11 of the D array head 3 is repeated.

Here, for example, in a picture signal group consisting of 4096-bit picture signals, each plane signal (bit) is numbered from '0' to '4095' and transferred as described above. First, the image signal is stored in the memory device 15 consisting of a random access memory element (RAM), etc. Then, "0" to "511", "
“512” ~ “1023”, “1024” ~”
1 535', "1536" ~ "204"
7”, “2048””~’“2559”, “
2560 ”~” 307 1 ”, “ 3072
"~"3583", ""3584'"~"40
It is divided into 8 groups such as 95"". These are sequentially transferred to the shift register 16 starting from the first image signal of each group. That is, "0", "512"',
“1024”, “1536”, “2048”, “25
The image signals are picked up in the order of ``60'', ``3072'', and ``3584'' and transferred serially.After this, they are picked up in the order of ``l'', ``513'', ``1025'', and finally ``3071''. , “3583”,” 4
095'', and all data transfer processing is completed.

Such data replacement processing is performed not only in devices using LED array heads but also in various devices. To perform this processing, for example, as shown in FIG. 14, a predetermined amount of data is supplied from an image information source such as a page memory 18 to a transposition processing device 19.

Then, store this data in the random access memory element in the transpose processing unit 19 in address order. Then, specifying another address order to be picked up, read the transposed data from this element, and supply it to the LED array head 3, electrostatic recording head, or thermal head for high-speed recording. become.

However, in conventional transposition processing, all data is reduced to 1
It requires processing to write data one by one and then read it one by one, which has the disadvantage of hindering the speeding up of the processing speed of the device. Furthermore, in the transposition processing device, data must be stored once in the shift register 16 as shown in FIG. 13, and this operation also causes a delay in data transfer time.

Incidentally, it is efficient to perform data read/write processing by a microprocessor or the like in parallel in word units, for example, data units of 8 bits each.

Therefore, a device as shown in FIG. 15 has been considered.

This device receives in parallel data read out in 8-bit units from a memory 21 that stores all data, transposes the data according to a predetermined rule, and outputs it to a parallel line 22. The principle of operation is shown in FIG.

In FIG. 16, one line of data 16 in the memory is first divided into eight groups, .about.L8.

Data is read one word (for example, 8 bits) at a time from the beginning of each group. The order of reading is Wl
, W2, W3...W8.

Thereafter, data for one word is read out again from the first group L1, and the same operation is repeated. This data is sent through an 8-bit parallel transmission line 23 to a matrix data transposition processing unit 24. Transposition processing device 2
4 serially transposes this data one word at a time as shown in the figure, and transfers the data of each word in parallel to the shift register 22 (this is, for example, the eight arrays arranged in the LED array head 3 shown in FIG. 12). (corresponding to shift register 11). By repeating this operation, one line of data is divided into eight parts and all are transferred to eight shift registers. At this time, data is read and processed in word units, so the processing can be performed at high speed.

Returning to FIG. 15, the explanation will be continued. This matrix data transposition processing device 24 is provided with an addressable latch 27 that stores input data according to an address signal 26. Addressable latches 27 include latches 2 prepared on the data input side for the number of data to be input in parallel.
There are 711 to 27, 8, and 27o1 to 27o8 prepared on the output side as many as the data to be output in parallel. Note that in this example, for convenience of explanation, both input and output are 8.
It has a line configuration.

It is assumed that eight consecutive pieces of data of 8 bits per word are input to the matrix data transposition processing device 24 in FIG. 15 through parallel input lines. In this case, the addressable latch 27 located at the top in the figure
11, the first bits of each of eight consecutively input words are latched in order at the addresses in the order in which they are input. Similarly, the second bit of each word is latched in the next addressable latch 2712 in turn. The same shall apply hereinafter. In this way, eight words are input to eight addressable latches 2711-2718 with one bit allocated to each.

Next, the first addressable latch 272 .
Addressable latches 27o1 to 27o on the output side
The data that has just been stored is sorted and transferred one by one to 8. Each addressable latch 2781 on the output side
~27o8 will store the first bit of each word at their first address. From the second addressable latch 27.2 on the input side to each addressable latch 27.2 on the output side. ．． ~27o8, those 2
The second bit of each word will be stored at the second address. The same applies below.

In this way, each addressable latch 2701 to 2701 on the output side
Each word is stored one by one in the address order in 27o8. If these are read out in address order, each word will be output to the output line 22 in parallel. This operation is exactly as shown in FIG.

By performing the above-described processing, it is possible to improve the efficiency of data reading and transfer.

However, the device shown in this example requires that each addressable latch contain an address decoder for decoding address information. For this reason, there is a problem that the amount of circuitry increases as a whole.

Also, because there are many data lines between addressable latches, these wirings! J! Becomes a pheasant.

Furthermore, due to the complexity of both the circuit and wiring, there is a limit to the high integration of this transposition processing device.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a matrix data transposition processing device that can easily cope with high integration.

1. Means for Solving Problem 1 In the matrix data transposition processing apparatus of the present invention, as shown in FIG. 1, the storage means 31 are arranged in M rows and N columns. And these M×N storage means 315. ~3
N storage means 31□ to 3 belonging to the first row of 1o
, H input data in parallel to N
Book input means 321 to 32N and M×N storage means 3
,．． M recording means 31 belonging to the Nth column of ~31□ output data in parallel from ~31MN
Two data input/output means are prepared: book output means 331 to 33M. In addition, M×N storage means 31□ to 31
Same as the row direction shifting means 34 which extracts data from □ all at once and shifts them in the direction of increasing rows (downwards in the figure) (M×N storage means 31 □ to 3,
Retrieve data from IN all at once, in the increasing direction of columns (
A column direction shift means 35 for shifting in the rightward direction in the figure is prepared.

1. Description of the basic operation of the apparatus of the present invention The basic operation of this apparatus will be explained based on FIG. The figure shows an example where M=N=4 to simplify the explanation. That is, in the matrix data transposition processing device of the present invention, first, as shown in FIG. Data is input in parallel. The shaded area in FIG. 2 represents the storage means in which data is set.

Once the data has been set in the four storage means 31□ to 31□, these data are shifted in the direction of increasing rows using the row direction shift means 34, as shown in the figure.

At this time, the four storage means 31, to 3, belonging to the first row
The following data will be input. In this way, data is sequentially shifted in the row direction, and
New data is supplied to the four storage means 31, to 31□ belonging to the first row (c and d in the figure).

In this way, when data has been stored in all of the 4×4 storage means 31□ to 314, the four output means 33
．． ~33. starts working. As a result, the four storage means 3114 belonging to the fourth column are first
~31, data is read in parallel.

At the same time, the operation of the column direction shift means 35 is started, and the data is shifted column by column (f in the figure). Then, data in the third column is read out. Thereafter, data is shifted in the column direction and read out in the same manner (gSh in the figure).

The basic operation of the matrix data transposition processing device has been described above. Data for each column starting from the Nth column of the M×N storage means arranged in M rows and N columns is transferred in parallel by the column direction shift means 35. When data is output to the matrix data transposition processing device, the M input means input data in parallel to each of the M storage means in the first column of the M×N recording means. If prepared, different transposition processing operations are possible. This will be explained in detail in the section describing the second embodiment of the present invention.

"First Example" The present invention will be described in detail below with reference to Examples.

FIG. 3 shows a transposition processing device for matrix data according to an embodiment of the present invention. This device 40 uses 4×3 D-type flip 70 tubes 41□ to 4 and 3 in four rows (M=4>) and three columns (N=3”) as storage means. The input terminals of the D-type flip-flops 4, 1 to 4143 are connected to the outputs of 2-to-1 (2 to 1) transistors 42 prepared correspondingly to the respective input terminals. One select line 44 is connected to the two-to-one data selector 42. Also, one select line 44 is connected to the three two-to-one data selectors 42 corresponding to the three D-type flip-flops 41, 41, belonging to the first row. The upper input terminal in the figure is connected to the Jonin Kalines 45. to 45., and the four D
In the figure, the lower input terminals of the four 2-to-1 data selectors 42 corresponding to type flip-flops 41, -4141 have six-input color lines 46. ~464 are connected.

D-type flip-flop 41 belonging to the second to fourth rows
2. ~A total of 9 2-to-1 corresponding to 41 and 3 respectively
As for the data selector 42, the upper input terminal in those figures is connected to the output terminals of the D-type flip-flops 41 to 4133 in the same column in the previous row.

Furthermore, the lower input terminals in the diagram of the 2-to-1 data selector 42 corresponding to the D-type flip-flops 4112 to 41 in the second and third columns are connected to the D-type flip-flops in the same row and one column younger than them. Type flip-flop 4111-4,
It is connected to the second output terminal. A common clock signal 47 is supplied to the clock terminals of each of the D-type flip-flops 41□ to 41,3.

On the output side of the four D type flip-flops 41, 3 to 4143 belonging to the third column of this transposition processing device 40,
Useful Kaline 48. ~48. is connected. Also,
three D-type flip-flops 4 belonging to the fourth row;
On the output side of 1 to 4 and 3, there is a lower output color line 49. ~493
is connected.

The matrix data transposition processing device 40 in this embodiment is as follows:
It is formed on a wafer using semiconductor manufacturing technology. Friend Karain 46. ~464 and Kaline Shimode 49. ~493
Although formed during this manufacturing process, it is unnecessary in this embodiment. Therefore, in this embodiment, wire bonding is not performed between these lines and external connection terminals.

By the way, when the signal supplied to the select line 44 is "0", the 2-to-1 data selector 42 selects the data supplied from the upper input terminal in the figure and outputs it to its output side. Further, when the signal supplied to the select line 44 is "1", the data supplied from the lower input terminal in the figure is selected and output to the output side. Each D-type flip-flop 4111-4143 is updated to the signal state provided at its input terminal at the rising edge of clock signal 47.

Therefore, the signal supplied to the select line 44 is "0"
'', when the clock signal 47 is generated, as explained in FIG. The parallel data supplied to 453 is taken into this transposition processing device 40 and sequentially shifted in the row direction (downward in the figure).

At the point when the clock signal 47 has been generated for four pulses, the device 4
Fill 0 with data.

After this, the signal supplied to the select line 44 becomes "1"
can be switched to Then, when three pulses of the p-tsk signal 47 are generated, all the data becomes a transposed matrix and the right output column 48. ~484 (Fig. 2 e)
-h).

[Modification of the first embodiment] FIG. 4 shows a modification of the first embodiment. Transposition processing device 5 for matrix data in this modified example
0, the same parts as in FIG. 3 are given the same reference numerals, and their explanation will be omitted as appropriate.

Now, in this transposition processing device 50, 3×3 D type
Flip-flops 41□ to 4133 are used as storage means, but a 2-to-1 data selector is not used, and three-state gates 5 and 52 are used instead. Here, one three-state gate 51 is an element that becomes high impedance when the signal supplied to the select line 44 is in the "0" state, and the other three-state gate 52 is in the "1" state. This is an element that becomes high impedance.

The transposition processing device 50 of this modification is similar to the transposition processing device 4 described above.
Unlike 0, it has 4 x 3 memory means, so Jonin Kalines 451 to 458 and Rokuin Kalines 461 to 463
, Udem Kaline 48. ~483, and Kaline 4
9. -493 are all configured with 3 lines each.

However, as in the previous embodiment, the left-entry line 461 to
46° and lower kaline 49. ~49. is not used in this embodiment either, and therefore no external connection terminal is provided.

In the transposition processing device 50 of this modification, the previous D in the same row is
One of the three-state gates 51 described above is arranged between the output terminal Q of the type flip-flop 70 tube 41 and the input terminal of the D-type flip-flop 41 in the next stage, and the previous three-state gate 51 in the same column The other three-state gate 52 is located between the output terminal Q of the D-type flip-flop 41 in a row and the input terminal Q of the D-type flip-flop 41 in the next row.

Since the matrix data transposition processing device 50 has such a configuration, the signal supplied to the select line 44 is “
0'', when the clock signal 47 is generated, the parallel data supplied to the Jonin Kara lines 45. to 45. 50 and are sequentially shifted in the row direction (downward in the figure).When the clock signal 47 has generated three pulses, the device 50 is filled with data.

After this, the signal supplied to the select line 44 is "1"
can be switched to Then, when the clock signal 47 is generated for three pulses, all the data becomes a transposed matrix and the right output column 48. ~48. (Figure 2 e)
-h).

Although a D-type flip-flop is used as the storage means in the first embodiment and its modification, the present invention is not limited to this. That is, (i) instead of the D-type flip-flop, it is possible to use other types of flip-flops, such as JK flip-flops. This is because it follows the same principle as a normal one-dimensional shift register.

(11) Furthermore, the data shift circuit realized by a flip-flop can also be realized by a capacitor circuit such as that used in a dynamic RAM (random access memory).

(iii) Furthermore, it is also possible to make a modification as shown in FIG. In this matrix data transposition processing device 60 shown in FIG. Place it on the output side of the unit.

Here, the matrix data transposition processing unit 62 has the same configuration as, for example, the matrix data transposition processing device 40 described in the first embodiment.

Among the above, a device using a flip-flop as a transposition processing device for (i>matrix data) has the advantage that data transposition processing can be performed reliably no matter how slow the clock signal becomes. This is because, unlike charging a capacitor, there is no need to worry about a drop in the charging voltage over time.On the other hand, (ii) if a capacitor is used as a storage means, dynamic RA
It is possible to configure a device with a small number of elements in comparison to the storage capacity like M. (iii) If a high-speed serial-to-parallel converter or the like is used for data input/output, even if the constructed matrix becomes large, the number of pins for human data output can be reduced, and large matrices can be This is suitable for implementing a transposition processing device for matrix data to be processed into an IC. It is not necessary to reduce the number of pins to one pin each for input and output in this way.

"Second Embodiment" In the first embodiment and its modifications described above, after data is set in all the storage means as shown in FIG. The contents of data stored in the storage means are once emptied. And after this,
Process the following data. Therefore, in these devices,
When inputting data line by line in parallel, data input must be temporarily interrupted once M lines of data have been stored.

The second embodiment improves on these points and provides a matrix data transposition processing device that enables continuous input and output of data. The basic operation of the device of this second embodiment will be explained based on FIG. The figure shows an example where M=N=4 to simplify the explanation. In addition, in this figure, in order to contrast with FIG. 2, the same parts as in FIG. 2 are given the same reference numerals.

Now, in the matrix data transposition processing device in this second embodiment, first, as shown in FIG. 6a, input means 321 to
32. , the four storage means 3, .
3114 to input data in parallel. The hatched or dotted areas in FIG. 6 represent storage means in which data is set.

Four storage means 31, to 313. Once the data have been serrated, the row direction shift means 34 is used to shift these data in the direction of increasing rows, as shown in the figure. At this time, the four storage means 3, to 31 belonging to the first row
, the following data will be input. In this way, data is sequentially shifted in the row direction, and new data is supplied to the four storage means 3, to 31□ belonging to the first row (c and d in the same figure).

In this way, 4X4 notes, key means 3, 1-3144
When data has been stored in all the four output means 3
3. ~33. starts working. As a result, the four storage means 3, . . .
314. Data is read out in parallel from.

Along with this, the column direction shift means 35 and the input means 711 to 7
The operation of , is also started, and data is input and shifted column by column (f in the same figure). Then, data in the third column is read out. Thereafter, in the same manner, inputting data in the column direction and reading out previously inputted data are performed all at once (g and h in the figure).

After all the data for the four lines previously input are transposed and output in this way, all the storage means 3111-
3144 will be filled with data for the next four columns (FIG. 1). In this state, as shown in FIG. J, the row direction shift means 34 is used to shift these data in the direction in which the rows increase. As a result, first, the data stored in the four storage means 3141 to 31,4 belonging to the fourth row is output as transposed data. At this time, the first
Row storage means 31, to 3, . The next new row of data is stored in (k in the same figure). Input of data in the row direction and output of transposed data are performed as described above (see FIG. 7).The same applies hereafter.

FIG. 7 shows a schematic configuration of a matrix data transposition processing device in this second embodiment. This device 7
0 is composed of a data transposition processing section 71 and a multiplexer 72, and is formed on one chip. Parallel data is supplied to the data transposition processing unit 71 on both the upper and left sides in the figure, and the data is sequentially stored inside the data transposition processing unit 71 by the row direction shift means or column direction shift means described above. shift will take place. At this time, the data transposed processing unit 71 outputs the transposed data in parallel from the left side or the bottom side in the figure. The multiplexer 72 selects one of these and outputs it to the outside as transposed data.

FIG. 8 shows the matrix data transposition processing device 70 shown in FIG.
This figure shows the specific configuration of .

This device 70 has three rows vertically (M=3) and three columns horizontally (N
=3) 3×3 D type flip-flops 81,
1-818. is used as a memory device.

Each D-type flip-flop 8, 1-818
．． There are two corresponding input terminals for each input terminal.
The output of the two-one data selector 82 is connected. 2
One select line 84 is connected to the tool data selector 82 . Also, 3 corresponding to the three D type flip-flops 8, 1 to 8113 belonging to the first row.
The upper input terminal of the two-to-one data selector 82 in the diagram has an input line 85. ~853 are connected and three D-type flip-flops 8111-8 belonging to the first column
In the diagram of the three 2-to-1 data seven receivers 82 corresponding to 131, the lower input terminals also have input lines 851 to 8.
53 is connected. Regarding the total of six 2-to-1 data selectors 82 corresponding to the D-type flip-flops 812 and 8133 belonging to the second and third rows,
In those figures, the input terminals on the second side are D-type flip-flops 8, 1 to 812 . . . in the same column in the previous row. is connected to the output terminal of Furthermore, D in the second and third columns
Type flip-flops 8,...818. The lower input terminal in the 2-to-l data selector 820 diagram corresponding to
They are connected to the output terminals of the younger D type flip 70 tubes 8111 to 8132 in the same row and one column. Each D type flip-flop 81,1 to 8133
A common clock signal 87 is connected to the clock terminal of
is being supplied.

Three D-type flip-flops 813 . belonging to the third column of this transpose processing device 70 . ~813. On the output side of l, there is a right-output color line 88. ~883 are connected. Also, three D-type flip-flops 8 belonging to the third row
131-810. On the output side of the lower output line 891~
89. is connected.

Right side lines 881-883 and bottom lines 891-8
9. are grouped corresponding one line at a time, and the two-tool data selectors 711 to 7 forming the multiplexer 72
23.

The basic operation of the data transposition processing section 71 in this matrix data transposition processing device 70 is the same as the circuit shown in FIG. 3, and therefore its explanation will be omitted.

"Modification of Second Embodiment" FIG. 9 shows a modification of the second embodiment. Transposition processing device 9 for matrix data in this modified example
0, the same parts as in FIG. 8 are given the same reference numerals.

This transposition processing device 90 also uses 3×3 D type flip-flops 81, -8133 as memory devices, but does not use a 2-to-1 data selector, and instead uses three-state gates 9, 92. is used. Here, one three-state gate 91 is an element that becomes high impedance when the signal supplied to the select line 84 is "0'', and the other three-state gate 91
The gate 92 is an element that becomes high impedance in the "L" state.

The transposition processing device 90 of this modification also has the above transposition processing device 7.
0, the input lines 851-853 are the D-type flip 70 knobs 81, ~8, 8.812 in the first row and first column.
0.81 and 1, so that data can be input from the top and left sides of the figure. Also, the D type flip-flops 81, ~8 in the third row
1 and the data output from the D-type flip 70 knobs 81,1 to 81,3 in the third row are output to the outside as final transposed data.

The basic operation of the device 90 of this modification is the same as the circuit shown in FIG. 4, so its explanation will be omitted.

According to the matrix data transposition processing device of the second embodiment or its modification described above, the data processing speed per unit time, that is, the throughput, is doubled compared to the device of the first embodiment or its modification. , efficient data processing becomes possible.

Although the second embodiment and its modifications also use a D type flip-flop as the storage means, the invention is not limited to this. That is, (i) instead of the D-type flip-flop, it is possible to use other types of flip-flops, such as JK flip-flops.

(ii) Furthermore, the data shift circuit realized by a flip-flop can also be realized by a capacitor circuit such as that used in a dynamic RAM (random access memory).

(iii) Furthermore, as shown in the first embodiment, the fifth
It is also possible to make modifications as shown in the figure. That is, the number of external connection terminals can be reduced by using a high-speed serial-to-parallel converter 61 or a high-speed parallel-to-serial converter.

In addition, in the apparatus of the second embodiment or its modification, instead of efficiently creating transposed data, it is also possible to perform mirror image transformation of the data to be transposed. FIG. 1O shown in correspondence with FIG. 7 shows such a transposition processing apparatus 100 for matrix data. This device 10
0, the arrangement order of the supplied parallel data is reversed depending on whether the supplied parallel data is input from the top side or from the left side in the diagram of the data transposition processing unit 71. Therefore, in the diagram of the data transposition processing unit 71, the data output from the right side and the parallel data output from the bottom side are also arranged in opposite directions.

The multiplexer 72 selects a desired one of these and outputs it to the outside.

``Effects of the Invention'' As described above, according to the present invention, since the data transposition process is performed using the storage means with M rows and N columns, the wiring in the A and B parts of the device becomes regular, making it easy to integrate into an IC. There are advantages.

[Brief explanation of drawings]

FIG. 1 is a principle diagram showing the basic configuration of the present invention, FIG. 2 is an explanatory diagram for explaining the basic operation of the device of the present invention, and FIG. 3 is a diagram of matrix data in the first embodiment of the present invention. A block diagram of a transposition processing device, FIG. 4 is a block diagram showing a matrix data transposition processing device as a modification of this embodiment, and FIG. 5 is a block diagram showing a modification of the data input/output section of these devices. , FIG. 6 is an explanatory diagram for explaining the basic operation of the device in the second embodiment of the present invention, FIG. 7 is a schematic configuration diagram of the matrix data transposition processing device in the second embodiment, and FIG. The figure is a block diagram showing a specific configuration of a matrix data transposition processing device in the second embodiment, and FIG. 9 is a block diagram showing a matrix data transposition processing device as a variation of the second embodiment. FIG. 10 is a schematic configuration diagram of a matrix data transposition processing device that can alternatively select transposed data and its mirror image transformed data, and FIG. 11 is a schematic configuration diagram showing an example of a recording device using LEDs. 12 is an explanatory diagram for explaining a conventional method of inputting data to an LED array head, and FIG. 13 is an explanatory diagram for explaining a method of processing data between a memory device that stores image information and each shift register. Explanatory diagram of no-go, No. 14
The figure is an explanatory diagram showing the general configuration of a transposition processing device and its peripheral devices, Fig. 15 is a block diagram of a previously proposed transposition processing device for matrix data, and Fig. 16 is the operating principle of this proposed device. FIG. 31... Storage means, 32... Input means, 33... Output means, 34... Row direction shift means, 35... Column Direction shift means, 40.50.60.70.90.100... Matrix data transposition processing device, 42.82... 2-to-1 data selector, 45... Jonin Kaline, 46...Friend Kaline, 48...Fukui Kaline, 49...Shimoyama Kaline, 5, 52.9, 92 Old...Three State Gate , 72...Multiplexer, 81...D type flip 70 knob. Applicant: Fuji Xerox Co., Ltd. Agent

Claims (1)

[Claims] 1. M×N storage means arranged in M rows and N columns, and each of the N storage means belonging to the first row of the M×N storage means in parallel. Enter data into N
a book input means, and an Nth one of the M×N storage means.
M output means for outputting data in parallel from M storage means belonging to a column; and row direction shifting means for taking out data from all of the M×N storage means at once and shifting it in the direction of increasing rows. and a column direction shift means for extracting data from all of the M×N storage means at once and shifting the data in the direction of increasing columns. 2. M arranged in M rows and N columns by column direction shifting means
When data for one column from the Nth column of ×N storage means is output in parallel, the data is output in parallel to each of the M storage means of the first column of the M×N storage means. 2. The matrix data transposition processing device according to claim 1, further comprising M input means for performing input.