JP2957448B2 - Data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-dimensional bit map of image data to be printed in a printing apparatus such as a plotter or a printer having a plurality of printing mechanisms capable of simultaneously printing at least in a moving direction of a recording medium. Means for transferring data to the printing mechanism.

[0002]

2. Description of the Related Art In such a conventional printing apparatus, two-dimensional bitmap data of image data to be printed is transferred or converted to a printing mechanism using a CPU to calculate data to be printed.

[0003]

However, in such a printing apparatus, the two-dimensional bit map data to be printed on the memory has the bit arrangement in the row direction corresponding to the data bits in the memory, and the recording medium. When printing is performed simultaneously in the moving direction of the recording medium in the case where the direction corresponds to the direction orthogonal to the moving direction of Is effective in increasing the transfer speed. In a conventional device that performs firmware using a byte addressable CPU in which one address corresponds to one byte, the processing speed is reduced. The present invention has been made in view of the above points, and an object thereof is to solve these disadvantages.

[0004]

Means for achieving the object is to provide two-dimensional bitmap data of the image data to be printed on a path for transferring the two-dimensional bitmap data to a printing mechanism, by performing forward printing and reverse printing. , A converter for converting the row and column of the bitmap data, and a storage for storing at least one block of matrix-converted data, and printing corresponding to the storage output. To transfer to the mechanism.

That is, eight or more shift registers corresponding to the row direction of the bitmap data are arranged in eight or more rows in the column direction, and the shift registers in each row are configured to be byte-addressable. The shift register can be substituted by multiplexing the output of each D-type flip-flop, but is not realistic in view of hardware simplification. The last-stage bit or the first-stage bit of the shift register in each row is configured to be byte-addressable with respect to the converted storage device. In order to support forward printing and reverse printing, it is possible to configure the shift register of each row so that it can be shifted to both left and right rows.However, in order to simplify hardware, a bit map is used. LSB to MSB of data are LSB of shift register
.. MSB correspond to L of the bitmap data.
A set of multiplexers that enables the case where SB to MSB corresponds to the MSB to LSB of the shift register is provided.

[0006]

Next, the operation will be described. Each output bit of the multiplexer is connected to a corresponding input bit of the shift register in each row. The control of the multiplexer is programmable. Since the input bits of the shift register are byte addressable with respect to the bitmap data, the shift register is selected and written by the decoder. Instead of a decoder, an address generator may be configured by a counter or the like so as to support a memory IO type DMA, so that sequential access is possible. When the writing for the desired number of rows is completed, all the shift registers start shifting. The output of the last stage is stored in the memory in synchronization with the shift clock. The stored data is sequentially called in accordance with an external print signal and transferred to the print mechanism.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a detailed view of a portion ○ in FIG. In FIG. 1, a data converter for controlling forward printing and reverse printing is provided on a path for transferring two-dimensional bitmap data of image data to be printed to a printing mechanism portion, and a line for the bitmap data. It has a converter for converting a column and a storage for storing at least one block of data after matrix conversion, and transfers the data to a printing mechanism corresponding to the storage output. In the description, it is assumed that the shift register in the row direction is set to 32 bits, and the shift register is arranged for eight rows in the column direction. Therefore, the multiplexer for supporting the preceding bidirectional printing is 32 bits. The control is specified as a command from external logic.

In this assumption, there are 32 byte-addressable shift registers 4, and the write control is performed by decoding one chip sector signal and five external address and write signals. I do. The writing, holding, and shifting operations of each shift register are performed by controlling a three-to-one multiplexer at the preceding stage of each register by two control signals M1 and M2. In the writing to the storage device, the completion of the writing to the 32 shift registers 4 is automatically detected, and the writing is performed 32 times in synchronization with the shift clock 7.
During writing 32 times, a busy signal (shift status signal) is output to prevent writing to the shift register. In this example, a FIFO (first-in first-out) memory 9 is used as a storage device. F
The reading from the IFO memory 9 is performed by an external logic that generates print timing, and one read corresponds to the timing of printing one dot in the moving direction of the printing mechanism.
In the figure, the part corresponding to the printing mechanism is substituted by an 8-bit D-type flip-flop. FIG. 3 shows a flowchart from the start of printing to the end of printing.

[0009]

According to the printing apparatus, the number of prints to be printed on the memory is 2.
In the case where the dimensional bitmap data has a row direction bit arrangement corresponding to the data bit sequence of the memory and further corresponding to a direction orthogonal to the moving direction of the recording medium,
When printing is performed simultaneously in the moving direction of the recording medium, it is effective to convert the bitmap data in advance so that the bit arrangement in the column direction corresponds to the arrangement of the data bits in the memory in order to increase the transfer speed. . According to the present invention, the processing can be performed at a higher speed than in a conventional apparatus that performs firmware using a byte addressable CPU in which one address corresponds to one byte.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a detailed view of a circle portion in FIG.

FIG. 3 is a flowchart.

[Explanation of symbols]

Reference Signs List 1 Data multiplexer for bidirectional printing 2 Sequence of multiplexed data of 1 3 Control signal of 1 4 Shift register for 1 row 5 2-bit signal for controlling writing, shifting and holding of shift register 6 From the previous stage 7 Shift clock 8 Control block 9 FIFO memory 10 D-type flip-flop 11 External logic for reading FIFO memory and generating latch signal

Claims (1)

(57) [Claims] 1. A data converter for controlling forward printing and reverse printing on a path for transferring two-dimensional bitmap data of image data to be printed to a printing mechanism, and a line for the bitmap data. A data transfer device, comprising: a converter for converting a matrix and a column; and a storage for storing at least one block of data after matrix conversion, and transferring the data to a printing mechanism corresponding to the storage output.