JP2644749B2 - Driver IC for light emitting diode array - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode array type electrophotographic printer, and more particularly to a driver IC used for a light emitting diode array head of a recording light source.

[Conventional technology]

In a light-emitting diode array drive circuit, when a high-density array is used, the density of connection points with a driver IC that drives the array also increases, making the connection difficult. In order to avoid this, a method is employed in which the extraction electrodes of the array are alternately drawn out on both sides of the array in a staggered manner by one dot. Accordingly, driver ICs are arranged on both sides of the array. Driver IC
Has a drive circuit corresponding to each element of the light-emitting diode array, but in general, in order to reduce the number of input terminals, light-emitting data is generally input serially from one or several places and output to each drive circuit. .

Now, consider the case where the same driver IC is arranged and driven on both sides of the light emitting diode array, as shown in FIG. In the figure, a data input terminal I of a driver IC1 comprising a register R for serial-parallel conversion and a driver D is located point-symmetrically from the center of the LED array LED on both sides of the array, and the data shift direction S is reversed. become. In order to arrange the data order in the light emitting diode array, it is necessary to reverse the order of the input data of one of the driver ICs, which is troublesome in data scanning. For this reason, a driver IC for bidirectional data scanning is used so that data scanning can be performed from either the left or the right.

FIG. 4 shows the configuration of the driver IC. SR
_{1 to} SR _n are a bidirectional shift register group for sequentially taking in serial data from n locations, LATCH is a latch for temporarily holding data which is serial-parallel converted and output by each shift register, and G is a light emission data. A gate that opens and closes the driver D and defines the light emission time of the light emitting diode array to be driven.

Each of the shift registers SR ₁ to SR _n particularly to a logic circuit configuration shown in FIG. 5. It has two series of shift registers composed of flip-flops FF whose shift directions are opposite to each other. When the terminal LD to enter data, for example, by inputting direction switching signal "1" from the terminal L /, select upper shift register captures sequentially in synchronism with Shifutokurotsuku the S ₁ direction. When RD is used as a data input terminal, a “0” signal is applied to terminal L / and S ₂
Capture data in the direction. The operation of the conventional bidirectional scan driver IC shown in FIG. 4 will be further described. When a latch strobe signal is input from the terminal LST at the time when data is taken into a predetermined register position, the data in the shift register is latched. Held in circuit LATCH. When a driver strobe signal is input from the terminal DST during the holding period, the driver D conducts based on the held data. That light emitting diode array flashes which is connected to the terminal Q ₁ to Q _N.

[Problems to be solved by the invention]

The above-mentioned conventional driver IC has a flip-flop circuit for the shift register in order to make the data shift direction bidirectional.
Twice as many numbers are required as in the case where the FF is unidirectional. This has been a problem of the prior art in that the driver IC has to be enlarged and the size of the light emitting diode array head on which the driver IC is mounted increases, resulting in an increase in cost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a driver IC for a light emitting diode array that can reduce costs and realizes bidirectional data scanning with a small number of register circuits.

[Means for solving the problem]

According to the present invention, a data bus is extended by extending the n data input terminals, and a register block consisting of n registers connected to the data bus and ordered by an array is repeatedly provided, and m register blocks are provided. The above object is achieved by obtaining bidirectionality with a bidirectional timing generator that enables

[Action]

In the present invention, the data itself moves and repeats input and output to and from a serial register as in the related art, instead of obtaining directionality.
The input timing to the register block affects the directionality. Since the timing signal is generated to make only the m register blocks bidirectional, the circuit size of the timing generator is smaller than that of the conventional bidirectional data shift.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the configuration of the driver IC of the present invention, and FIG. 2 is a timing chart of the operation. Data bus n bits DB in FIG. 1 to the input terminal of _{DI 1 ~DI n, RB 1 ~RB} m is the m registers Bro poke, LATC
H is a latch of nm (= N) bits, BSR is a bidirectional shift register, G is an AND gate, and D is a driver for driving the light emitting diode array.

Each of the register blocks RB _{1 to} RB _m includes n individual registers R ₁ , R ₂ , R _3, ..., R _n , and the individual registers and the register blocks are arranged from left to right in ascending numerical order. Each individual register has an input terminal, an output terminal, and an enable terminal. The input terminal is connected to the data bus of the data input terminal of the same number, the output terminal is connected to LATCH, and the enable terminal is parallel in the same register block. Wiring is performed and the signals are collectively connected to the output of the flip-flop FF of the BSR. The BSR does not transfer the image data itself as shown in the above-described conventional example, but captures the image data from the data bus DB to the register block.
A timing signal is transferred so as to be sequentially enabled in accordance with RB _{1 to} RB _m . The shift signal is composed of two series of m-stage shift registers whose shift directions are opposite to each other, and a digital signal “1” is supplied to a terminal L /. , "0", the shift directions S ₁ and S ₂ can be selected.

First, consider the case where data scanned so as to output the young order of the data on the left terminal Q _1. At this time, a signal of “1” is given to the terminal L / to select the upper shift register of the BSR. In synchronization with the clock signal input from the terminal CLK at the start of the scan, as shown in FIG. 2, given a panel-like start pulse signal having a width of one clock terminal LSP, this is the S ₁ by the clock Sent in the direction of each stage
Output from FF. This output signal CK are sequentially fed to the register block, the register block sequence i.e. RB _1, RB ₂ from the left, is enabled to the order of ... RB _m.

Image data that serial number order and a data input terminal _{(DI 1, DI 2, ...} DI m) through wiring connections to match the number sequence, at all synchronized to said clock, supplied to the data bus DB to the n-bit units. Image data input at the first clock
_{D 1, D 2, ... D} n , since only register block RB ₁ by the synchronization input of the start pulse is enabled, the image data D ₁ to the register R ₁ constituting the register block, image data in the register R ₂ D ₂ is the image data D _n is taken into the register R _n. In the second clock, the transfer of the start pulse, only the register block RB ₂ is enabled, captured the image data D (n + 1), D (n + 2), ... D2 n from the left of the register block RB ₂ to the right . When such an operation is sequentially repeated and the m-th clock is reached, N bits (N = n × m) are stored in all of the m register blocks from left to right in ascending order.

Next, a case where data scan as order young data is output to the inverse direction of the data scan or right output terminal Q _n to the aforementioned. Terminal L of bidirectional shift register BSR
/ Is set to "0", the switch SS is switched to the dotted line side, and the lower shift register is selected. If a start pulse similar to the above is given to terminal RSP in synchronization with the clock, a signal that enables the register block together with the clock
CK are sequentially outputted in the direction of S _2. This is the second
In as shown in FIG lower half, this time in synchronization with the clock, the register block starts from the rightmost RBm, sequentially enabled to leftmost RB _1, the data bus DB
, The image data is taken in n-bit units. At this time, by performing an input connection to the data bus in the order of the number of terminals DI and image data serial number in the reverse order to the image data from the right of R _n in the individual register of each register block to R ₁ left There are stored, exactly the opposite position from that of the aforementioned operating the BSR to S ₁ direction. Thus, as was said that the youngest image data to the driver output terminal Q _N is output, the order of the data and the output terminal number is output reversed,
The direction is opposite to the data scanning direction described above.

In the above description, the bidirectionality of data scanning is given by the operation up to the register block. The register required for this is the sum of the bidirectional shift register BSR and the register block RB, and is n · m + 2m. On the other hand, in the conventional method shown in FIG. 4, the total number of registers for obtaining bidirectionality is 2 nm. And less. In the case of n = 8 bits, the configuration is reduced by 37%, the size of the driver IC is correspondingly reduced, and the cost is reduced.

Further, in the conventional example, the number of data elements is doubled due to the bidirectionality. In contrast, in the present invention, the number of input terminals for the start pulse is increased by only two, and the number of terminals is reduced. This also contributes to reducing the IC size. As described above, the driver IC according to the present embodiment is reduced in size due to the reduction in the circuit scale and the number of input terminals, and the cost is reduced.

〔The invention's effect〕

As described above, according to the present invention, since the IC size can be reduced as compared with the related art, a convenient driver IC having a bidirectional data scanning function can be manufactured at low cost.

[Brief description of the drawings]

1 is a block diagram showing an embodiment of a driver IC of the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, FIG. 3 is a diagram showing a conventional example of driving a light emitting diode array, FIG. 4 and FIG. 5 are configuration diagrams of a conventional driver IC. BSR: Bidirectional shift register, DB: Data bus, R
B _{1 to} RB _m ...... Register block, LSP, RSP ...... Start pulse input pins.

Continuation of the front page (72) Inventor Toshio Iizuka 5-1-1, Hidaka-cho, Hitachi City Inside the Cable Research Laboratory, Hitachi Cable, Ltd. (56) References JP-A-61-41269 (JP, A)

Claims (1)

(57) [Claims] A first register for sequentially storing image data; a second register for temporarily storing image data filled in the first register; and a second register for temporarily storing the image data. In a driver IC for a light emitting diode array having a driving means for switching based on image data, a first register means includes a register block including an n-bit data bus and n registers connected to the data bus. A driver IC for a light-emitting diode array, comprising: a plurality of register block groups; and an m-stage bidirectional shift register for creating timing for sequentially taking in data into the register blocks.