JPS5919291A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To attain high speed while keeping high S/N, by decreasing the capacity of the 2nd data line. CONSTITUTION:The 2nd data lines I/O(0), I/O(1) are arranged in parallel with the 1st split data lines D00, D01, D02, D03. Thus, the load capacity of the I/O(0) and I/O(1) is decreased remarkably because only transistors relating to less number of switched corresponding to the split number of one data line are connected. Thus, a signal extracted on the I/O(0), I/O(1) at high speed with switches SW00, SW01, for example, is outputted to the 3rd data line I/O with the selection of any of switches SWY0, SWY1 controlled with a Y decoder YDEC, and becomes a data output Dout with a read/write control circuit RWC.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device suitable for achieving high S/N and high speed.

Conventionally, as a means to achieve high S/N, the patent application 1986-0
There is 81042. That is, as shown in FIG.
])o1. DO2, f) o3 or Die, D
ll.

D12. Dta, and connect these divided data lines to a second data line l via a switch 5WOO, etc.
10(0), l10(1), l10(2), l1
This is a method for exchanging data with 0(3). In this method, since the first data line is subdivided, the load capacitance seen from the memory cell is reduced accordingly, making it possible to achieve a high S/N ratio or high speed. However, in this method, the second data lines l10(0) and l10(1).

Since many transistors related to many switches are connected to l10(2) and l10(3), these second
Since the load capacity of the data line becomes large, there is a limit to increasing the S/N and speed.

Note that W is a word line, and XDEc and YDEC are
and Y decoder, RWC is read/write controller, MC is memory cell, wE is write enable signal, D
I indicates input data, and Dout indicates output data.

An object of the present invention is to provide a memory device that reduces the capacitance of a second data line.

FIG. 2 is a conceptual diagram of the present invention. That is, the second data line l10 (OL l10(υ, divided first data line, [)oo, Dot, DO2, ]) as
etc. are arranged in parallel. By doing this, the load capacitances of I, 10(0), and l10(1) are as shown in Figure 1 because only the transistors related to a small number of switches corresponding to the number of divisions of one data line are connected. It's much smaller in comparison. Therefore, for example, depending on Hasuichi 5WOO, 5WO1, etc., l10(0), l10
The signal sent out at high speed to (1) is sent to the Y decoder YDEC.
One of the switches 5Wyo and 5WY1 controlled by is selected and output to the third data line I10, and the data output f)ou
It becomes t.

FIG. 3 shows a more detailed embodiment of FIG. 2, with sense amplifiers SAt, SA2 . This is an example in which SAs are provided. This allows the signals appearing on each data line to be amplified at high speed. It is obvious that depending on the case, a configuration in which nine sense amplifiers are removed as appropriate can be used.

FIG. 4 is a modification of FIG. 2 in which the data lines are configured as paired lines.

The fifth to seventh examples are specific examples of memory cells in which the data lines are formed by paired lines. FIG. 5 shows a flip-flop type memory cell MC used in static AM. FIG. 6 shows an example of a twin memory cell disclosed in, for example, Japanese Patent Application No. 59783/1982, and FIG. 7 shows a memory cell as disclosed in, for example, Japanese Patent Application No. 49-148056.

FIG. 8 shows a memory cell (Qpen 13it Lin) described as a conventional example in Japanese Patent Application No. 49-148056.
This is an example in which the present invention is applied to an eCell.

FIG. 9 shows a specific embodiment of FIG. 3 in which a 1-bit memory cell is composed of one transistor and a capacitor. The outline of the operation is as follows.

First, when the word line W is selected, a minute read signal is output from each cell MC to the data lines DOO, DIO, D2G, ])3° to which the memory cells MC are connected.

At the same time, a pulse voltage is also applied to the dummy word line DWL, and the data line to which the dummy cell DC is connected])oo,
I)to, D20, ])ao is outputted from each dummy cell DC to the intermediate level of the output signals '1'' and 'OH from the memory cell MC.These data, %
1l) Output signals of the pair of lines such as oo and DIG are transmitted to the sense amplifier SAi by turning on the data line GCL, and are differentially amplified by the sense amplifier SAI. This amplified signal is output to the sense amplifier SAI by turning on either the signal -IOCo or IOc1 under control by the address signal. For example, if the signal l0CO is turned on, the pair of wires DI
The respective signals of O and DIO and the pair of lines p30 and D30 are output to the corresponding sense amplifier SA2. Similarly, if the signal l0Cx is turned on, the pair of wires 1)o
o and])oo and the signals of the pair of lines D20 and D20 are output to the corresponding sense amplifier SA2. In this example, the wiring pitch of the pair of wires I/0 (0) and I/O (0) and the pair of wires l10 (1) and I/O (1) are decoded using signals l0CO and l0C1 to make the wiring pitch dog. be. This method uses pair I/O(0) and I/O
This is effective when O(0) or the like is formed in the second layer of A4, which is relatively difficult to manufacture with a large wiring pitch, as in Japanese Patent Application No. 56-0810'42. Furthermore, the signal l0C2, l
The same applies to the operation of the circuit 5AIO (details in the figure are omitted for simplicity) controlled by 0C3.

As is clear from the embodiments described above, in the present invention, the load capacitance of the data line is reduced compared to the conventional one, and as a result, the load capacity of the data line is reduced, resulting in a high S/
High speed can be achieved while maintaining N.

[Brief explanation of the drawing]

Figure 1 is a conventional configuration diagram, Figures 2 to 9 are embodiments of the present invention, Figure 2 is a conceptual diagram, Figure 3 is a current circuit diagram of one embodiment, and Figure X is a circuit diagram of another embodiment. The circuit diagrams, FIGS. 5 to 7 are block diagrams of memory cells, and FIGS. 8 and 9 are circuit diagrams of other embodiments. ])oo, ])ot, DO2...first data line, I/O(0).

Claims (1)

[Scope of Claims] 1. A device comprising a divided first data line group and a second data line for exchanging data with the first data line group via a first switch. , a semiconductor memory device in which the second data line is arranged in the same direction as the first data line group. 2. The semiconductor memory device according to claim 1, wherein the first switch is controlled by an address. 3. Claim 1, wherein the second data line is connected to the third data line via a second switch controlled by the address.
The semiconductor memory device described in Section 1. 4. Said 1. 2. The semiconductor memory device according to claim 1, wherein the second and third data lines are paired lines. 5. The semiconductor memory device according to claim 1, wherein a sense amplifier is connected to each of the first data line group. 6. Said No. 2. 2. The semiconductor memory device according to claim 1, wherein a sense amplifier is connected to each or one of the third data lines. 7. The semiconductor memory device according to claim 1, wherein the second data line is formed of a metal of a different layer from the metal forming the word line or the data line.