JPS6146918B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory circuit using an insulated gate field effect transistor (hereinafter referred to as MOS transistor).

As a conventional memory circuit using one transistor cell, there is a circuit having a configuration as shown in FIG.
Here, for simplicity, the X-address is A0, A
It has a 3-bit configuration of 1 and A2, and unnecessary parts for the following explanation will be omitted. The MOS sense amplifier circuit 5 is composed of cross-connected MOS transistors Q ₁ and Q ₂ . A pair of digit lines 1 and 2 (referred to as a digit line pair) are connected to a pair of output points of this sense amplifier circuit, and a decoder 6 receives inputs A0 to 2 (referred to as a digit line pair).
Word lines AL0, AL1, AL2, AL3 by A2
Select to drive. Decoder 7 also receives inputs A0 to A2 and selects word lines AL4, AL5, AL6, and AL7. Memory cells C ₀ to C ₇ connected to each word line are accessed by selectively turning on transistor Q ₁₀ depending on the level of this word line. Dummy bus lines AD0 and AD1 are controlled by addresses 2 and A2, respectively.

In the memory circuit shown in Figure 1, the word line AL0
is selected and a signal voltage as shown in Figure 2 is applied, if cell _C0 stores "high", it will give a "high" differential output to digit line 1, and if it is "low", it will give a "high" differential output to digit line 1. gives a “low” difference output. At this time, the dummy bus line AD1 is selected and provides an intermediate difference output between the "high" difference output and the "low" difference output to the digit line 2. The MOS sense amplifier circuit 5 operates upon receiving the difference signal between the digit line pair 1 and 2.

Conventionally, in this type of memory circuit, as the number of bits increases, the number of memory cells connected to the digit line pair 1, 2 increases, and the number of memory cells connected to the digit line pair 1, 2 increases.
The load capacitance of MOS sense amplifier circuit 2 has increased, and as a result, the difference signal of the MOS sense amplifier circuit cannot be obtained large. Also, in order to obtain the same difference signal, the capacity of the memory cell itself must be increased,
As a result, there was a drawback that the chip size increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory circuit in which the load capacitance of a digit line is reduced and the detection sensitivity is improved.

The memory circuit according to the present invention includes a plurality of sense amplifiers each having a pair of input terminals, and a first digit line consisting of two digit lines arranged on one side of each sense amplifier and running parallel to each other. a second digit line pair consisting of two digit line pairs arranged on the opposite side of each sense amplifier and running parallel to each other; and a pair of input terminals of each sense amplifier. and each first pair of digit lines arranged between each pair of switching elements, and the pair of input terminals of each sense amplifier and each second pair of digit lines. a second pair of switching elements disposed between them to simultaneously control each switching element of the first pair of switching elements; and a first control line that simultaneously controls each switching element of the second pair of switching elements; and a second control line for simultaneously controlling the elements, each of the digit lines is connected to a plurality of memory cells, and the memory cells connected to the digit lines of each first digit line pair are different from each other. Also regarding memory cells that are word lines and are connected to word lines different from the memory cells connected to the digit lines of the second digit line pairs, and connected to the digit lines of the second digit line pairs. The control line is connected to different word lines, and a selected one of the first and second control lines is set to an active level, thereby rendering a pair of switching elements connected thereto conductive. According to the present invention, since the memory cells assigned to one sense amplifier are connected in a distributed manner to two pairs of digit lines, the number of memory cells connected to each digit line pair is halved, and the number of memory cells assigned to one sense amplifier is reduced by half. The capacity of the digit line is also significantly reduced. Furthermore, in the present invention, in order to prevent the storage information from being destroyed when the memory cell connected to each digit line of the digit line pair that is not connected to the sense amplifier is accessed by the selected word line during operation, In addition, by connecting the memory cells assigned to one sense amplifier to different word lines, data destruction can be prevented and a highly practical memory circuit can be realized. Further, in the present invention, the same pair of digit lines are arranged in parallel and on one side of the sense amplifier, and the other same pair of digit lines are also arranged in parallel on the other side of the sense amplifier. The layout is also efficient because the two switching element pairs that connect the two digit line pairs and the sense amplifier's pair of input terminals can be efficiently arranged, and these two switching element pairs can be controlled with two control lines. Therefore, it is suitable for high density. Further, according to the present invention, a one-transistor cell is used.
In MOS memory, each MOS sense amplifier circuit that amplifies the difference signal from the memory cell has two pairs of digit lines, and each of these digit lines is connected via two pairs of MOS transistors that act as switching elements to transmit the signal. , is connected to a MOS sense amplifier, and a first control line is connected to the gates of the pair of MOS transistors, and this control line becomes active level when a first signal controlled by a certain address signal is input. A second control line is connected to the other pair of gates, and a second signal having the opposite phase of the first signal is inputted to the control line, so that when the memory is accessed, the gate of the MOS transistor is connected to the second control line. The input signal turns off the pair of MOS transistors, disconnects the pair of digit lines on the non-selected side from the MOS sense amplifier, and disconnects the pair of digit lines on the selected side from the pair that remains on.
A memory circuit is obtained which is connected to a MOS sense amplifier via a MOS transistor and transmits a difference signal from a selected memory cell to the MOS sense amplifier circuit. In this case, the number of memory cells connected to each digit line is halved, and the load capacitance of the digit line is substantially reduced by electrically isolating the digit line on the non-selected side. As a result, there is an effect that the difference signal of the MOS sense amplifier can be increased without increasing the memory cell capacity.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is an embodiment of a memory circuit according to the present invention. For simplicity, we will use the X-address as A
It has a 3-bit configuration of 0, A1, and A2. Further, parts unnecessary for the explanation of the present invention are omitted. Digit lines 1 and 2 parallel to each other constitute one digit line pair, and digit lines 3 and 4 parallel to each other constitute another digit line pair. The MOS sense amplifier circuit 5 is composed of cross-connected MOS transistors Q ₁ and Q ₂ . This MOS sense amplifier circuit 5 includes memory cells C ₀ , C ₂ and a dummy cell DS _{0 .}
Digit line 1 connected to MOS transistor Q ₃
Connect to the gate of MOS transistor _Q1 through the input/output of . Furthermore, the digital line 2 connected to the memory cells C ₁ , C ₂ and the dummy cell DS ₁ is connected to the sense amplifier circuit 5 via the input/output of the MOS transistor Q ₄ .
Connected to the gate of MOS transistor _Q2 . Similarly, the digit line 3 connected to memory cells C ₄ , C ₆ and dummy cell DS ₂ and the digit line 4 connected to memory cells C ₅ , C ₇ and dummy cell DS ₃ are connected to each other.
It is connected to the gates of MOS transistors Q ₂ and Q ₁ of sense amplifier circuit 5 via MOS transistors Q ₅ and Q ₆ , respectively. MOS transistor
The gates of Q ₃ and Q ₄ buffer address A2.
Control lines DSL ₀ that receive outputs via AB ₂ are connected to each other, and control lines DSL ₁ that receive address 2 outputs via buffer ₂ are connected to the gates of MOS transistors Q ₅ and Q ₆ . Here, when the control line DSL ₀ or DSL ₁ is at an active (high) level, the transistors Q ₃ , Q ₄ or Q ₅ , Q ₆ become conductive.
Address outputs AL0 to AL3 of the decoder 6 are connected to word terminals of memory cells _C0 to _C3 , respectively,
Addresses 0 and A0 are buffers DA and DA, respectively.
A dummy cell is created by the output AD0 and AD via DA′.
Applied to the word terminals of DS ₀ and DS ₁ .
Similarly, address outputs AL4 to AL7 of decoder 7 are connected to the word terminals of cells _C4 to _C7 , and addresses 0 and A0 are output via buffers _DA2 and _DA2 '.
It is connected to the word terminals of dummy cells DS ₂ and DS ₃ by AD ₂ and AD ₃ . Here each memory cell
As shown in Fig. 4, one end of _C1 was connected to the power supply _VDD and the other end of the capacitor _C0 was connected to the word terminal W, and the source was the digital terminal DT.
Consists of FETQ ₀ . In the memory circuit shown in FIG. 3, when address bus line _AL0 is selected, address bus line AL0 is selected as shown in FIG.
Before the selection signal voltage is applied to , DSL1 changes from a "high" level to a "low" level, turning off MOS transistors Q ₅ and Q ₆ . In addition, DSL0 maintains a “high” level, and the MOS transistor
Q ₅ and Q ₄ remain on. As a result, digit line pair 3, 4 is electrically disconnected from MOS sense amplifier 5, and digit line pair 1, 2 is disconnected from MOS sense amplifier 5.
Connected to MOS sense amplifier 5. When a signal voltage is applied to the address line AL0, a high difference output is provided to the digit line 1 when the cell _C0 is "high", and a low difference output is provided when the cell C0 is "low". At this time,
Dummy bus line AD1 is selected and provides digit line 2 with an intermediate difference output between the high difference output and the low difference output. The MOS sense amplifier circuit 5 operates upon receiving the difference signal between the digit lines 1 and 2. Also
Similarly, when MOS transistors Q ₅ and Q ₆ are turned on, reading is performed after addressing. In this way, in the present invention, the digit line pair is separated into two, thereby reducing the number of memory cells connected to each digit line pair by half, and by electrically isolating the digit line pair on the non-selected side. , it is possible to substantially reduce the load capacity of the digit line. As a result, there is an excellent effect that a large difference signal of the sense amplifier can be obtained without increasing the memory cell capacity. Note that the present invention is not limited to the above-mentioned embodiments, but can also be applied to sense amplifier circuits,
The present invention can be applied to any type of memory cell or the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional memory circuit. FIG. 2 is a timing diagram for explaining the circuit operation of FIG. 1. FIG. 3 is a diagram showing an embodiment of a memory circuit according to an embodiment of the present invention, and FIG. 4 is a circuit diagram showing a memory cell. FIG. 5 is a timing diagram for explaining the circuit operation of FIG. 3. 1, 2, 3, 4...digit in, 5...MOS
Sense amplifier circuit, 6, 7...X decoder, A0,
A1, A2...X address, AL0-AL7...address bus line, AD0, AD1, AD2, AD3...dummy bus line, DSL0, DSL1...digit line separation signal bus line.

Claims (1)

[Claims] 1 A plurality of sense amplifiers each having a pair of input terminals, a first digit line pair consisting of two digit lines arranged on one side of each sense amplifier and running parallel to each other, and each sense amplifier A second digit line pair consisting of two digit line pairs arranged on the opposite side to the one side and running parallel to each other, a pair of input terminals of each sense amplifier and each first digit line pair. a first pair of switching elements disposed between each of the pair of digit lines for connecting the pair of digit lines; A first control line that simultaneously controls each pair of second switching elements arranged in the second pair of switching elements, a first control line that simultaneously controls each switching element of the first pair of switching elements, and a first control line that simultaneously controls each switching element of the second pair of switching elements 2 control lines, each of the digit lines is connected to a plurality of memory cells, and the memory cells connected to the digit lines of each of the first digit line pairs are different word lines, The memory cells connected to the digit lines of each second digit line pair are connected to different word lines, and the memory cells connected to the digit lines of each second digit line pair are also connected to different word lines. A memory circuit characterized in that a selected one of the first and second control lines attains an active level, thereby rendering a pair of switching elements connected thereto conductive.