JPS59191660A - Program debugging device - Google Patents

Abstract

PURPOSE:To recognize both the process and rate of task execution and to improve the program debugging efficiency by writing the address of a branching destination into a trace memory when the control right is shifted from a monitor to a prescribed program. CONSTITUTION:The output of a comparator 14 is set at H when the coincidence is obtained between the address data on an address bus 15 and the address obtained when a branching instruction latched previously by an address latch 13 is executed. Then an FF17 sets the output of the comparator 14 when the inverse MEMR of a memory read signal is produced during the generation of an instruction fetch signal M1. Then the output of the comparator 14 is set at L. The output of a gate 19 is set at L with the inverse MEMR when a task start address is delivered from a CPU during generation of the next signal M1. The MEMR is turned into the write signal of a trace memory 2 and writes the task start address on the bus 15 via a buffer 22.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a zero-gram badge device in a microcomputer system.

[Background technology]

Conventionally, there has been a method for debugging microcomputer systems by using an insert editor instead of a CPU. However, actually the CPU
If you connect and run the CPU and the CPU goes out of control for some reason, it is not possible to confirm where it went out of control. Also, when using an in-circuit emulator, the in-circuit emulator has a trace function and will not run out of control, but when you actually connect a CPU and run it for debugging, if a runaway occurs, it will cost you a lot of money. The problem was that it took a long time to clean.

Therefore, the present inventors have proposed a zero-jiram device that can actually connect a CPU to perform the conversion and is also equipped with a toss function.

Figure 1 shows the overall schematic configuration of the proposed Nozuji Ramji Baduji device, in which 111 is the CPU;
+21 is trace method, fa+l, t CRT,
f4+ is the cow board, (5) is the system path line, (
6) is a parallel input interface, these components constitute a jojiramjiba soge device,
It is connected to the system bus (7) on the target side via the parallel input interface (6).

The data on the target side system bus (7) is written to the trace memory (2) at the timing of the target side microcomputer system side, and the written contents of the trace memo (January 2) are written on the cow-board. (
The data is read out by the operation 4) and displayed on the CRT (3). Figure 2 shows a specific circuit of the configuration shown in Figure 1. Writing data from the target side to the trace memo 1/2) requires a switching signal from the CPU 1l+ (Fig. (not shown), and the set switching signal provides a switch. At the same time, it disables the buffer (91) and enables the output of the parallel input circuit (61) that constitutes the parallel input interface (6),
The data bus connected to each RAM (21)...
The data bus (51) from the Ufi+ side is switched to the system path line (7) on the target side.

It also enables the selection switching and attenuation of each RAM (21), the count bias (8), and the write signal of the RAM (21). In other words, target side IOR, 40W, MEMR
. . . are logically summed by the OR gate (10), and the logical product of this gate output and the switching signal is
D)f-) (12), and the gate outputs thereof are inputted to the corresponding circuits as the above-mentioned gate and write signals. Also, the OR game of the 1000 select signal from the CPU1l+ and the switching signal) (The logical sum output from 11 gates becomes the 10 select signal for the RAM (2t) mentioned above.And I10 The address count buffer (8) ff: is incremented by the control signal, and as a result, the data from the lid side of the tarp is sequentially stored in the RAM (21)... and this storage, i.e. Tracing is terminated by inverting the switching signal.Then, the traced data is stored in the address count buffer (8) by setting the address by the I10 control signal, and is transferred to the RAM ( 21)...

In this way, according to the circuits shown in FIGS. 1 and 2, it is possible to trace the operating state of the CPU on the tarp/lid side, eliminating the need to use an inserter unit, and also making it possible to trace the operating state of the CPU on the tarp/lid side. Urator timing and actual CPU
Depending on the timing difference when connecting the CP
This means that it is easy to investigate the cause of the runaway that occurs when U is implemented.

By the way, in this case, when one process consists of multiple tasks (hereinafter referred to as tasks), in order to increase processing efficiency, when processing is done in time division, in order to know the execution rate of each task, In the case of the above configuration, a large capacity memory is required in the trace memory (21), and it is troublesome and inconvenient to know the ratio.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned problems, and its purpose is to easily recognize the task execution process.
To provide an O'J RAM exchange device which can recognize the execution rate of a task and improves the efficiency of one requisition.

[Disclosure of the invention]

Figure 3 shows an embodiment of the present invention. In the figure, 031 is an address latch, and this address latch 03) executes a branch instruction for the monitor in charge of real-time processing to pass control to a task. Then, the address at the time of this branch instruction is input to the data bus (input from the country and latched by the ■10] node signal. (14) is a comparator, and this comparator 1 node 04) is the address latch. Input the address data inputted in step (13) to input terminal B, input the reset data on the at-speed bus (15) to input terminal A, and input the address data inputted to both input terminals A and B. This is for comparison purposes only.
Together with 31, this constitutes a means for detecting an address at the time of fetching an instruction. 0η is a D-type flip-flop (I7), and this D-type flip-flop (I7) is used to set the output of the above-mentioned comparator (round) when the above-mentioned instruction is read. Then, if the address data input to comparator 04) match, this D type free 1 software 0
・The Q output of Sozu0no is set to be L".Furthermore, the matching type clear signal θη is output from the CPU (not shown) by the command signal M1 and the memory read signal ME.
The NAND gate (I8
) is used as the gate output, and the input data is selected at the rising edge of the clock. Traceme'tl: l f2 (is a memory write signal input terminal WR and a chitsuzu selector signal input terminal C8 are commonly connected, and the output of the above-mentioned NAND) f-to08),
The above type clears the logical sum with the Q output of Florazu θno.
R gate 09) obtained by 7. The m'f-t output is used as the respective input signal. In other words, D-type flip-up D.
Sod07) and OR gate 19) constitute a writing means. @) is the attoshi counter, and this attoshi counter (
20) is a signal that inverts the gate signal of the above-mentioned OR gate with an inverter (21), and outputs the count data as a trace head address (2). There is.

Therefore, if the address buster on the address bus (I5) shown in FIG. 4(a) matches the address at the time of execution of the branch instruction, which is latched in advance by the address counter (13), then the address shown in FIG. d), the converter (14
The output of j becomes "Hl/. Then, when the instruction signal MEM1 is generated at the time when the instruction signal MEM1 shown in FIG. 4(b) is generated, the NAND gate (18)
The output of
0tsu occurs as shown in Fig. 4(e), and at the rise of the D-riff, a D-type flip occurs (1η is]
The output of the converter 04) is discharged, and the Q output becomes -L as shown in FIG. 4(f). Now, when the next instruction flag/subsignal M1 is generated, the start address of the task shown by diagonal lines in FIG. 4(a) is output from the CPU (not shown). Due to the memory read signal MEMR at this time, the output of the OR gate Q91 becomes 1L", and this $L
The signal that becomes `` becomes 0 in the address counter 120), and the output of OR)f-)09) in Figure 4 (
The trace memory F IJ +21 serves as the chip select signal of the trace memory (2) shown in g) and the write signal of the trace memory (2). The start address is written.Then, the address counter (2[1)
At the rising edge of O, the address counter (2
0) will add 1 to the count contents, and as a result, the address of (2) will be incremented. At this time, the controller (14) is not outputting a matching signal, so the ◇ output of the D-type flip-flop (17) becomes 1Hl, and the trace mode continues until it becomes "L#" again.
No data is written to 2). Furthermore, the fourth
Figure (C) shows the output signal from the CPU (not shown). In addition, TR0M in Fig. 3 is a trace-on signal, and this trace-on signal continues until the D type free 1
This clears the Suzufu O1 Ritsu (17) and address counter (company).

Furthermore, although the circuit for reading data from the storage memory (2) is omitted in the above embodiment, it goes without saying that the data may be read using an appropriate circuit.

By the way, the embodiment shown in Figure 3 writes the start address in the trace memo 2), but the timer interrupt,
Depending on the location where task execution is interrupted by other external interrupts, operations may not work properly if an interrupt occurs. In this case, if it is known in advance, it is sufficient to disable the interrupt, but if it is not known and the system is not operating normally, it is difficult to determine where the problem is.

Therefore, the embodiment shown in FIG. 5 is such that the start address of the task and the atlas executed immediately before the occurrence of the interrupt are written into the I-L memory (2).

This embodiment is based on the circuit shown in FIG. (23) is usually a CPU (
When the address latch signal ALE shown in FIG. 6(b) rises from the source (not shown), it is input as the latch enable signal ALE shown in FIG. 6(i) via the NAND gate 1(c). , and latches the data on the address bus 06) shown in FIG. 6(a).

When the interrupt request signal lNTR shown in Fig. 6(e) rises, the D type
(23'l is the next address latch signal ALE)
This is to prevent any further delay when the voltage rises.

That is, the execution address immediately before the interrupt indicated by diagonal lines in FIG. 6(a) is left unretched. The D-type Ritsu Flo-Rizu 2151 uses the address latch signal AL.
At the rising edge of E, the Q output of the D-type frits flora is t.
%, and sets its own Q output to H# and Q output to 1LI. Also, D-type Frizz-Flo Rizuri (to)
The Q output of is logically ANDed with the Q output of the D-type flip-flop O2'J (I) by AND gate e26), and this AND output is logically ANDed with the gate output from NAND gate 08) by OR gate (19). A logical sum is calculated. Therefore, the memory read signal MEMR shown in the 6th m6(d) becomes effective as a memory read signal for the D-type fritz Florazu (when the Q output of 2[51 becomes 1L, trace memo January 2). At the same time, when the Q output of the D-type Furi Sozu Florazu becomes H#, the gate of the barrier wire is closed, and the Q output latches (
When the OE terminal of the main part) becomes 1L", the data from the main part), that is, the address before the interrupt shown by the diagonal line in FIG. The captured data is written when the memory read signal MEMR becomes valid as shown in FIG. The CLR terminal of 24) is connected via an AND gate 9) to the D-type flip flop shown in FIG. 6(h).
The Q output of 5) is input and the D-type fritz flow 1 sozu (24)
is cleared, the straddle υ child (3) becomes latchable, and the next address 5 prediction signal ALE causes the trace function f(
The data input in step 2) is switched to the buffer (4) side. When tracing the start address of a task, it is carried out in the same manner as in the embodiment of FIG.

Note that FIG. 6(C) shows the instruction fetch signal M1, and FIG.
g) indicates D-type frizz florazu□□□ glue o1riku.

〔Effect of the invention〕

As described above, the present invention provides a microcomputer system that processes a plurality of D-grams in real time.
The monitor is equipped with means for detecting an address at the time of fetching an instruction to branch to the 106 RAM from a t monitor that manages the jogram, and means for writing the address of the branch destination after the detection into the trace meter at the time of fetching the instruction at that address. Since the branch destination address is written in the trace memory when control is transferred from the Ogram to a predetermined Ogram, the execution process of the task can be easily recognized by simply reading the address data written in the trace memory. It is also possible to recognize the execution rate of tasks, which improves the efficiency of program batching.

[Brief explanation of the drawing]

Fig. 1 is a schematic configuration diagram of the conventional example, Fig. 2 is a specific circuit diagram of the main parts of the same as above, Fig. 3 is a circuit diagram of an embodiment of the present invention, Fig. 4 is a time chart of each part of the same as above, and Fig. 5 The figure is a circuit diagram of another embodiment of the present invention, and FIG. 6 is a time chart of each part of the same. 1η is D-shaped
(e) is an address counter, Ml is an instruction feed signal 13, and MEMR is a memory read signal. l+-cni: two, =

Claims (1)

[Claims] In a microphone computer system that processes fi + multiple zu0jirams in real time, there is a means for detecting an address at the time of fetching an instruction to branch to zu0jiram from a monitor that manages zu0jirams, and a means for detecting the address of the branch destination after the detection. and a means for writing to the trace memory when an instruction at that address is fetched, and the branch destination address is written to the trace memory when control is transferred from the monitor to a predetermined column. zu0jiramjibatsuji device.