JPS59190706A - Limiter circuit - Google Patents

Abstract

PURPOSE:To obtain a limiter circuit which has an optionally settable input conversion gain and a gain regardless of a control input by decreasing the gain of the limiter when the gain of an amplifier increases with a control voltage. CONSTITUTION:Transistors (TR) Q1-Q3, resistances R1-R5, and bias power sources V1 and V2 constitute an amplifier whose gain is controlled by the control voltage VC of a control voltage source VC. Further, TRs Q4-Q9, resistances R6 and R7, and constant current cources I 1- I 3 constitute a limiter whose gain is controlled by a bias power source V3 according to the control voltage VC. In this case, the gain of the amplifier increases with the control voltage VC and the limiter decreases in gain. Thus, a limiter circuit which has the input conversion limiter level set optionally by the control voltage VC and has the constant gain regardless of the control voltage VC is IC- implemented suitably.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a limiter circuit, and relates to a limiter circuit suitable for use, for example, in a noise canceling circuit of a magnetic recording/reproducing device.

[Technical background of the invention]

Generally, in a magnetic recording/reproducing device (hereinafter referred to as a VTR), a video signal is recorded on a magnetic tape, and when the video signal is transferred, the S/N ratio of the reproduced signal is Therefore, the reproduced signal is passed through a noise canceling circuit to improve its S/N ratio. This noise canceling circuit is shown in Figure 1.Hereinafter, the circuit of Figure 1 will be explained. The operation of this circuit will be explained with reference to FIG. 2 showing operating waveforms at each point.

The reproduced video signals that are input to the terminal fl) are shown in Figure 2 (5).
The image contains noise as shown in the figure. This signal is transmitted through a delay device (2) and a bypass filter (HPF) (3).
is input. The output of HP F (3) is shown in Figure 2 (B)
The noise component of the signal is extracted here. However, the l high frequency component 8H of the signal is also extracted at the same time. The amplifier (4) and limiter (5) extract only the noise component from this noise component and the high-frequency components of the signal.
). Here, if the input-equivalent limiter level at the input end of amplifier a (4) is Vt, then vL' is the limiter level of limiter (5) in terms of a long sword, and GA is the gain of amplifier (4). It is.

becomes. This input conversion limiter level Vy is shown in Fig. M2 (
As shown in B), the noise level pp (peakt
o peak ) If the value is chosen slightly larger than the limiter (5), the output of the limiter (5) will contain a noise component and a slight signal high frequency component (see Figure 2 (q)).The output of the limiter (5) By subtracting from the reproduced video signal that has passed through the delay device (2) in the subtracter (6), a reproduced video signal output from which noise has been removed can be obtained from the terminal (7) (
(See Figure 2 η). The delay device (2) is thus used for timing the two inputs to the subtractor (6). That is, if τDL, rHPF, τA, τL=i are the group delay times of the signals in the delay device 12), HP F (3), amplifier (4), and limiter (5), respectively, then τDL=τHPF + τA + τL (2 ) The delay time of the delay device (2) is determined so that the following holds true.

By the way, in order to remove noise most effectively and minimize distortion of the reproduced video signal in the noise canceling circuit shown in FIG. 1, the following conditions should be satisfied. That is, if the input ratio to the subtractor (6) is 1:1, then equation (2) and Vt, = Np-p
(3) (IPF -GA-GL (=G)
-GDr, (4) Equation (3) above, (4)
It is necessary to satisfy the formula. Here, Np-p is the pp value of noise in one reproduced video signal, and GHPF,
GL and GDL are the gain in the passband of HP F (3), the gain of limiter (5), and the delay device (2), respectively.
is the transmission gain of If the above conditions are not satisfied, for example, if Vt > Np-p, the noise will be completely removed, but the removal of the high frequency components of the signal will be large (and the reproduced waveform will become dull. <N1)-p, noise is not completely removed. Further, in the case of G to QDL, noise is similarly not completely removed.

As mentioned above, in order to effectively operate the noise canceling circuit, it is necessary to satisfy both equations (3) and (4).

FIG. 3 shows an example of the case where the conventional noise canceling circuit as described above is integrated into an integrated circuit. In the circuit shown in Fig. 3, a differential amplifier is used as a limiter, and VL
Σ240mVp-p, so the amplifier gain is selected from 4 to 6 so that the noise level N (4o~6゜mVp~p) at the noise input terminal (8) matches the input potential limiter level VL. It is designed to fit the (3) type firefly south foot. Also, the gain and group delay from the endogenous video signal input to the reproduced video signal output via the delay device (2) are
'L are selected so as to match each other, and R is set so as to satisfy equation (2) and fJ equation.

[Problems with background technology]

In the circuit shown in Fig. 3, by improving the characteristics of the 7-band band system of the VT circuit or by using other noise reduction circuits (such as those using line correlation gain 1), the noise input terminal (8) When the noise level decreases or when the noise level increases due to unforeseen factors, the input converted limiter level remains constant, so the most effective noise canceling effect cannot be achieved.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned points, and the input conversion limit level can be set arbitrarily, and the key is constant regardless of the control input, and it is suitable for integrated circuits.
It is an object of the present invention to provide a limiter circuit suitable for use in a noise canceling circuit of I-1.

[Summary of the invention]

The present invention cascades an amplifier whose gain increases or decreases according to a control input and a limiter whose limiter level is constant and whose gain decreases or increases according to the control input,
The limiter circuit is configured such that the input end of the amplification H bowl is the input end, and the output end of the limiter is the output end.

[Embodiments of the invention]

1. An embodiment of the limiter 1 circuit according to the present invention is described in the 4th section.
This will be explained with reference to the circuit diagram shown in the figure.

In FIG. 4, Ql to Q are transistors.

R1 to R are resistances, and ■1 to ■3 are bias electrolytic corrosion.

Vc is a control voltage source, and I1 to I3 are constant current sources. Here, the transistors Q to Q3 and the resistors
to R5, bias voltage, source V, , control voltage f1. An amplifier whose gain is controlled by a control voltage Vc of Vc is configured. Still transistors Q4 to Q
9 and resistance. , 7, constant current sources I to I3, and bias power supply V3 constitute a limiter whose gain is controlled by the control voltage Vc.

In this case, the gain of the amplifier increases as the control voltage Vc increases, while the limiter is controlled to decrease its gain. Further, the resistance values of the resistors R5, R6, R, . . . are all set to be equal. Furthermore, a constant current meter It.

■2. Current value of I3 11. I2. 1 = for I3
There is the following relationship: I,=2I2=2I, (5).

Next, let's analyze the circuit shown in Figure 4.

As mentioned above, if the resistance values of the resistors R5 to R5 are equal and this 1-direction fRE is assumed, and the characteristics of the transistors Q3 to all Q5 are the same, then their collector currents 1c are all equal, and it becomes as follows. Here, VBE is the base-emitter voltage drop of the transistors Q3 to Q5.

The gain GA of the amplifier is Qh = −−1c Rt' (7
)kT. Here, q is 'lltM of electrons, k is the Boltz-Mambo number, T is the absolute temperature, and RL is the resistance value of the resistors R3 and R4.

Also, the limiter gain (jL is 2Ic (8). Therefore, the afi-gain GT of the amplifier and limiter is (from the method and equation (8), GT = Uh-GU, regardless of the control n!l voltage Vc It becomes constant.

Next, find the input-referred limiter level VL at the input terminal (Iυ) of the amplifier. First, the Beka-referred noise level ■L' of the differential limiter consisting of transistors Q6s and Qv is (this value is approximately 240rnVp-p at T=350"C).
) and be humiliated. Therefore, the input conversion limiter level VL is as follows. 00 equation (6) becomes 1 (the displacement of the person becomes 1), and the input conversion limiter level vL can be controlled by the control voltage Vc. Also, since the limiter output signal level obtained at the output terminal a4 is as small as several 6 mVp-p, , 4th
The signal may be amplified to a desired level using a differential amplifier (1 to 1) as shown by the dotted line in the figure.

FIG. 5 is a diagram showing an embodiment in which the limiter circuit according to the present invention is applied to a noise canceling circuit for V T jL.

In Fig. 5, Qv is an input terminal and t2a is an output terminal.

(c) is the HPF, and (to) is the delay device. Also, Q11 to Q23 are To2/Jista, R81 to R2□ and RBX
T resistance, Vn+ r VB2 r vCC power supply
'), I,, 7'7 to 114 are constant current sources. Note that the current value of the constant current source 114 is set to -the current value of the constant current source 113. In this case, in order to operate at a low voltage, an amplifier using a PNP transistor and a limiter using an NPN transistor are used. In addition, by inputting the reproduced video signal together with a DC bias to the base of the load transistor Q23 of the limiter, the transistor Q23
The emitter end of the adder also functions as an adder.

In the circuit of Figure 5, the external resistor RE of the integrated circuit (c)
By changing the value of XT, the noise input terminal αEO
The input converter 7L'j can be set arbitrarily, and the gain from the noise input terminal CI to the reproduced video signal output terminal is always constant. Therefore, the external resistor RE
can be set, and it is possible to perform the noise canceling operation most effectively in any VTR.

(Effects of the Invention) As described above, according to the present invention, when the gain of the preceding stage amplifier is increased (decreased) by the control voltage, the gain of the subsequent stage limiter is decreased (increased) by the same control voltage. By doing so, it is possible to provide a +)6-triangle circuit that can arbitrarily set the input conversion limiter level depending on the control voltage, has a constant gain regardless of the control voltage, and is optimal for integration into an integrated circuit.

When used in a noise canceling circuit for a VTR, it is possible to easily set the most effective noise canceling operation for a VTR that handles all noise levels.

[Brief explanation of the drawing]

Figure 1 shows -513'Fc of a conventional noise canceling circuit.
2 is a diagram showing waveforms of various parts of the circuit in FIG. 1, FIG. 3 is a circuit diagram showing an example of a conventional noise canceling circuit integrated into an integrated circuit, and FIG. 4 is a diagram showing the present invention. Figure 5 is a circuit diagram showing an example of a limiter circuit.
' ) is a diagram showing an example of the noise canceling circuit of l. ll...Input terminal, 12...Output terminal, Ql to Q,...Transistor, R1 to R2...River/resistance, ■,... ...Constant current source, ■ to ■3...Bias power supply, Vc...
...Control m pressure γ field. Agent Patent Attorney Kensuke Chika (and 1 other person) 1! J
Figure 1? figure

Claims (1)

[Claims] An amplifier whose gain increases (or decreases) according to a control input and a limiter whose limiter level is constant and whose gain decreases (or increases) according to the control input are connected in cascade, and the input terminal of the amplifier and the output terminal of the limiter are connected in cascade. a limiter circuit having an input terminal and an output terminal, respectively, comprising first and second transistors whose emitters having a collector load resistance as the amplifier are commonly connected, and connected between the emitter connection point and ground; using a first differential amplifier consisting of a first controlled current source controlled by the control human power,
The third limiter whose emitters are connected in common is the Atf limiter.
, a fourth transistor, a first constant current source connected between the emitter connection point and ground, and a third . a second constant current source having a current Ilb half that of the first constant current source connected to at least one collector of the fourth transistor; a second constant current source having a base connected to a bias power supply; and an emitter connected to the first control A limiter circuit characterized in that a second differential amplifier including a fifth transistor is connected to a second controlled current source having the same current directivity as the current source.