JPH0523082B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a limiter circuit, and relates to a limiter circuit suitable for use, for example, in a noise cancel circuit of a magnetic recording/reproducing device.

[Technical background of the invention]

In general, magnetic recording and reproducing equipment (hereinafter referred to as VTR)
In , video signals are recorded on magnetic tape,
Further, when reproducing the signal, the S/N ratio (signal-to-noise ratio) of the reproduced signal deteriorates due to modulation noise, sliding noise, reproduction amplification noise, etc. Therefore, the reproduced signal is passed through a noise canceling circuit to improve its S/N ratio. This noise cancel circuit is shown in FIG. The operation of this circuit will be explained below with reference to FIG. 2 which shows operating waveforms at each point in the circuit of FIG.

The reproduced video signal input through terminal 1 contains noise as shown in FIG. 2A.
This signal is input to a delay device 2 and a high pass filter (HPF) 3. The output of the HPF 3 is as shown in FIG. 2B, where the noise component of the signal is extracted. However, the high frequency component S _H of the signal is also extracted at the same time. Amplifier 4 extracts only the noise component from this noise component and the high frequency components of the signal.
and limiter 5. Here, if the input equivalent limiter level at the input end of amplifier 4 is V _L , then V _L = V _L ′/G _A (1) However, V _L ′ is the input calculation limiter level of limiter 5, and G _A is the input calculation limiter level of limiter 5. is the gain.

becomes. This input limiter level V _L is shown in Figure 2B.
As shown in , the noise level pp (peak to
If you choose slightly larger than the peak) value, the limiter will be 5.
A noise component and a slight signal high-frequency component are obtained in the output (see Fig. 2C). By subtracting the output of the limiter 5 from the reproduced video signal through the delay device 2 in the subtracter 6, a reproduced video signal output from which noise has been removed is obtained from the terminal 7 (see FIG. 2D). Here, the delay device 2 is used to time-align the two inputs to the subtracter 6.
That is, if τDL, τHPF, τA, and τL are the group delay times of the signals in delay unit 2, HPF 3, amplifier 4, and limiter 5, respectively, then the delay time of delay unit 2 is determined so that τDL = τHPF + τA + τL (2) holds. There is.

By the way, in order to remove noise most effectively and minimize distortion of the reproduced video signal in the noise canceling circuit shown in FIG. 1, the following conditions should be satisfied. That is, subtractor 6
If the input ratio to is 1:1, then equation (2) and V _L = Np-p (3) G _HPF・G _A・G _L (=G)=G _DL (4) Above equation (3), Equation (4) must be satisfied. however,
Here, Np-p is the noise p-p in the reproduced video signal.
_GHPF , _GL , and _GDL are the gain in the passband of the HPF 3, the gain of the limiter 5, and the transmission gain of the delay device 2, respectively. When the above conditions are not satisfied, for example when V _L >Np-p, noise is completely removed, but the amount of removal of high frequency components of the signal also becomes large and the reproduced waveform becomes dull. Also, V _L
<Np-p, noise is not completely removed. Similarly, when G≠G _DL , noise is not completely removed.

As described above, in order to effectively operate the noise cancel circuit, it is necessary to satisfy both equations (3) and (4).

An example of the case where the conventional noise canceling circuit as described above is integrated into an integrated circuit is shown in FIG. In the circuit shown in Fig. 3, a differential amplifier is used as a limiter, and since V _L is 240 mVp-p, the noise level N at the noise input terminal 8 (usually 40 to 60
The gain of the amplifier is selected to be 4 to 6 times so that mVp-p) and the input equivalent limiter level V _L match,
It is designed to satisfy equation (3). Furthermore, the gain and group delay from the input of the reproduced video signal to the output of the reproduced video signal via the delay device 2 are selected so as to match each other, and are designed to satisfy equations (2) and (4).

[Problems with background technology]

In the circuit shown in Figure 3, the noise level at the noise input terminal 8 was reduced by improving the characteristics of the VTR's tape/head system or by using other noise reduction circuits (such as those using line correlation). However, if the noise level increases due to some reason, the input converted limiter level remains constant, so the most effective noise canceling effect cannot be achieved.

[Purpose of the invention]

The present invention has been made in view of the above points, and the input conversion limiter level can be set arbitrarily.
Another object of the present invention is to provide a limiter circuit which has a constant gain regardless of the control input, is suitable for integration into an integrated circuit, and is suitable for use in a noise canceling circuit of a VTR.

[Summary of the invention]

In the present invention, an amplifier whose gain increases or decreases according to a control input and a limiter whose limiter level is constant and whose gain decreases or increases according to the control input are connected in cascade, the input terminal of the amplifier is used as an input terminal, and The limiter circuit is configured so that the output end is the output end.

[Embodiments of the invention]

An embodiment of the limiter circuit according to the present invention will be described below with reference to the circuit diagram shown in FIG.

In FIG. 4, Q ₁ to Q ₉ are transistors,
R ₁ to R ₇ are resistors, V ₁ to V ₃ are bias power supplies, V _C
is a controlled voltage source, and I ₁ to I ₃ are constant current sources. Here, transistors Q ₁ to Q ₉ and resistor R ₁
R ₅ to R 5 and the bias power supplies V ₁ and V ₂ constitute an amplifier whose gain is controlled by the control voltage V _C of the control voltage source V _C . Here, the transistor
Q ₁ and Q ₂ correspond to the first and second transistors in the claims, respectively, and are transistors.
Q ₃ and resistor R ₅ correspond to the first controlled current source.
These components constitute a first differential amplifier. Also transistors Q ₄ to Q ₉ and resistors
R ₆ , R ₇ , constant current sources I ₁ to I ₃ , and bias power supply V ₃ constitute a limiter whose gain is controlled by control voltage _VC . That is, transistors Q ₆ and Q ₇ correspond to the third and fourth transistors in the claims, respectively, and the constant current source I ₁
corresponds to the first constant current source, and constant current source I ₂ (or
I ₃ ) corresponds to the second constant current source. Furthermore, the bias power supply V ₃ corresponds to a bias power supply in the claims, the transistor Q ₄ and the resistor R ₆ (or the transistor Q ₅ and the resistor R ₇ ) correspond to a second controlled current source, and the transistor Q ₈ ( or Q ₉ ) corresponds to the fifth transistor. These components constitute a second differential amplifier. In this case, as the control voltage V _C increases, the gain of the amplifier increases, while the limiter is controlled to decrease its gain. Further, the resistance values of resistors R ₅ , R ₆ , and R ₇ are all set to be equal. Furthermore, constant current sources I ₁ , I ₂ ,
The current values I ₁ , I ₂ , and I ₃ of I ₃ have the following relationship: I=I ₁ =2I ₂ =2I ₃ (5).

Next, let's analyze the circuit shown in Figure 4.

As mentioned above, the resistance values of resistors R ₅ to R ₇ are equal, and this value is set as R _E , and if the characteristics of transistors Q ₃ to Q ₅ are equal, their collector currents I _C are all equal, and I _C = V _C −V _BE /R _E (6). Here, V _BE is the base-emitter voltage drop of transistors _Q3 to _Q5 .

The gain G _A of the amplifier is determined as G _A =q/4kT・I _C R _L (7). Here, q is the electron charge, k is the Boltzmann constant, T is the absolute temperature, and R _L is the resistance value of the resistors R ₃ and R ₄ .

Also, the gain G _L of the limiter is G _L = q/2kT・I・kT/q・1/I _C =I/2I _C (8
) becomes. Therefore, the total gain of the amplifier and limiter is
From equations (7) and (8), G _T becomes G _T =G _A・G _U =q/8kT・R _L I (9), which is constant regardless of the control voltage V _C.

Next, the input equivalent limit level V _L at the input terminal 11 of the amplifier is determined. First, transistor Q ₆ ,
The input-referred noise level V _L ′ of the differential limiter composed of Q ₇ is given by V _L ′=8 kT/q (10) (this value becomes approximately 240 mVp-p when T=350〓). Therefore, the input conversion limiter level V _L is as follows: V _L = V _L ′/G _A = (kT/q) ² ·32/I _C R _L (11). By substituting equation (6) into equation ( ₁₁ ), V _L = (kT/q) ²・R _E /R _L・32/V _C −V _BE (12) This means that the conversion limiter level V _L can be controlled. Also the output end
The limiter output signal level obtained in (12) is several hundred m
Since Vp-p is small, it may be amplified to a desired level by a differential amplifier 13 as shown by the dotted line in FIG.

FIG. 5 is a diagram showing an embodiment in which the limiter circuit according to the present invention is applied to a noise canceling circuit for a VTR.

In FIG. 5, 21 is an input terminal, 22 is an output terminal, 23 is an HPF, and 24 is a delay device. Also
Q ₁₁ to Q ₂₃ are transistors, R ₁₁ to R ₂₁ and
REXT is a resistor, V _B1 , V _B2 , V _CC are power supplies, I _11
I14 to I14 are constant current sources. Note that the current value of constant current source I ₁₄ is set to 1/2 of the current value of constant current source I ₁₃ . In this case, PNP
It uses a transistor amplifier and an NPN transistor limiter. Furthermore, by inputting a DC bias and a reproduced video signal to the base of the load transistor _Q23 of the limiter, the emitter terminal of the transistor _Q23 also functions as an adder.

In the circuit shown in FIG. 5, the input equivalent limiter level at the noise input terminal 26 can be arbitrarily set by changing the value of the external resistor REXT of the integrated circuit 25, and the input-equivalent limiter level at the noise input terminal 26 can be set to the reproduced video signal output terminal 22. The gain up to is always constant. Therefore, the noise level of a VTR using the noise canceling circuit shown in FIG.
The external resistor REXT can be set so that the input converted limiter levels at the noise input terminal 26 are equal, and it is possible to perform the most effective noise canceling operation in any VTR.

〔Effect of the invention〕

As described above, according to the present invention, when the gain of the amplifier in the previous stage is increased (decreased) by the control voltage, the gain of the limiter in the latter stage is decreased (increased) by the same control voltage. Therefore, it is possible to provide a limiter circuit that can arbitrarily set the input-converted limiter level by controlling the control voltage, has a constant gain regardless of the control voltage, and is optimal for integration into an integrated circuit.
Furthermore, when used in a noise canceling circuit for a VTR, it is possible to easily set the most effective noise canceling operation for a VTR having any noise level.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an example of a conventional noise cancel circuit, Figure 2 is a diagram showing waveforms of various parts of the circuit in Figure 1, and Figure 3 is an example of an integrated circuit of the conventional noise cancel circuit. 4 is a circuit diagram showing an embodiment of the limiter circuit according to the present invention, and FIG. 5 is a diagram showing an embodiment of a VTR noise canceling circuit to which the limiter circuit according to the present invention is applied. It is. 11...Input terminal, 12...Output terminal, _Q1 to _Q9 ...Transistor, _R1 to _R7 ...Resistor, _I1
I ₃ ... constant current source, V ₁ - V ₃ ... bias power supply, V _C ... control voltage source.

Claims (1)

[Claims] 1 Gain increases (or decreases) by control input
and a limiter whose limiter level is constant and whose gain decreases (or increases) according to the control input are connected in cascade, and the input terminal of the amplifier and the output terminal of the limiter are used as input terminals and output terminals, respectively. The amplifier includes first and second transistors having a collector load resistance and whose emitters are commonly connected, and a first transistor controlled by the control input connected between the emitter connection point and ground. A first control current source consisting of a controlled current source of
A differential amplifier is used, and the limiter includes third and fourth transistors whose emitters are commonly connected, a first constant current source connected between the emitter connection point and ground, and the third and fourth transistors. a second constant current source having a current value half that of the first constant current source connected to at least one collector of the transistor; a base connected to a bias power source; and an emitter connected to the first controlled current source. A limiter circuit characterized by using a second differential amplifier comprising a fifth transistor connected to a second controlled current source having the same current value.