JPS59189461A - Control system of storage device - Google Patents

Abstract

PURPOSE:To realize the optional number of combined divided storage part and one or an optional number of CPUs by controlling an output selector to control plural divided storage parts with a selecting signal. CONSTITUTION:A set of a control part 1a and a register 2a and a set of a memory 5a, a control part 1b, register 2b, and a memory 5b are operated as minimum units. An output selector 3 and input selectors 4a-4e are controlled to operate memories 5a and 5b as two independent storage devices in accordance with a CPU0 and a CPU1 respectively in a multisystem and to operate them as a storage device of memory 5a+memory 5b in accordance with the CPU0 in a single system.

Description

DETAILED DESCRIPTION OF THE INVENTION +a+ Technical Field of the Invention The present invention relates to an IT control system for a storage device used in an information processing system.

Background of ibl Technology In recent years, the F# information processing system has come to be used in a wide range of fields due to its development and spread. On the other hand, on the hardware side, large-scale integrated circuits (1
, SI, l Products such as microprocessors and large-capacity memories are provided at a low cost.
The main memory in this system requires large-capacity, high-speed memory, and is usually constituted by dynamic access memory (DRAM).The memory device is a collection of DRAM elements, an intermediate mounting unit such as a printed wiring board, and a plurality of intermediate In packaging units, the printed circuit board was housed in a common housing to constitute a device for each housing.In recent years, D) CAM based on LSI has improved in density along with other logic circuits, and the number of units per package has increased. The memory capacity has been increased by 1] to 256 kilobits (the capacity is 16 kilobits compared to the previous one).
Kb or 64Kb products are now available in the same size, and if 128 packages are implemented in an intermediate packaging unit, it can reach as much as 4 megabytes (MB). This 4M, B or device unit for example 32MB 7
Thailand; J 64MB is a large capacity (7) CPU + is a capacity that is used exclusively as an appropriate storage capacity. intermediate implementation unit such as IMB or 2
MB is often appropriate. However, providing multiple types of intermediate mounting units is undesirable from the viewpoint of manufacturing and maintenance based on testing.

(dl Structure of the Invention The purpose of the major invention is to solve the above-mentioned problems, and to implement implementations with a common large storage capacity even at the intermediate implementation unit level, and even with divided use corresponding to multiple CPUs, a single CPU This document is intended to provide a braking method for the device that can also be used for collective use.

tel Structure of the Invention The object of the present invention is to provide a plurality of divided memory sections, a plurality of corresponding access control means, and a means for selecting according to a selection signal provided above the address signal of each divided memory section. When configuring some storage devices and operating them in response to multiple externally connected central processing units (
In addition, when the corresponding divided storage section is accessed independently and separately by using the selection means that is reset to 0 according to an address signal that does not include a selection signal in each control means, multiple A storage device characterized in that the upper control means among the control means causes the selection means to select the divided storage section from among the plurality of divided storage sections under its control in accordance with a selection signal to access a part or all of the storage capacity of the storage device. This can be achieved by providing a control scheme.

(fl Embodiment of the Invention An Embodiment of the Invention ζ will now be described with reference to the drawings. The figure is a block diagram of a storage device control system in an embodiment of the invention. In the figure, la.

1b is a memory access control unit, 2a and 2b are address registers, 2aa and 2ba are lower bits, and 2ab
, 2bb are the top binods, 3 is the output selector (
81 (1, bars 4a, 4b, 4C, 4q, 4e are input selectors (MPX) and 5a, 5b are divided storage units (memories). In one embodiment of the present invention, the control unit 1a and the register 2a are respectively and memo IJ 5a, a control unit 1b, a register η2b, and a memory 5b as the minimum unit.The structure of the storage device is composed of two groups of dynamic random access memories (DRAMs). select (RAS), column access select (c
p-b), rai 1-ii ipuru (WE), address (
ADD), write data (WL), etc. using the selection button 7JI]. MPX4a is for manual selection of RAS, M
PX4b is for CAS selection, MPX4C is for WD selection, MPX4d is for ADD selection and MPX4
e is for selecting read data. Multiple CPUs with this
0. For ePUl, each group independently operates the memory IJ 5a and memory 5b as a multi-system.

In the case of a single system, address register 2a rochi 2
Address the storage unit 5a with aa, and 5Ei with 2ab.
RAS supply to 5a and 5b is selected by 1 and 3, and control is performed to select 5a or 5b.

For example, when 2aa is 0'', RAS is supplied to 5a by S E L3 and is not supplied to 5b. As a result, 5a is selected as the storage section. When 2ab is a1'', the reverse is true.

In the case of a multi-system, 2ab will never be 1''.

When it is "1", CPU0 has specified a storage area that is not implemented, which is clearly an error. For this reason, the RAS signal generated in 1a is always supplied to 5a as ASO. In addition, 1vlPX4a to e are set to 0 by the control unit 1a.
It is assumed that the value is set to 11111. Next, a plurality of divided storage units, here memo 145a.

5b are collectively allocated to the CPU 0 for use, the control unit 1a sets 1 to the MPX4a-e according to the initial setting control of CR"oo (not shown), and sets the memory 5b to the CPU0.
Operate a and b as a single system. CPU0
In response to the start signal from , each signal is created in the same way as when the system is operating as described above, and the bit added to the most significant bit of ADDO is used as a selection signal to perform SEW or selection operation to control RAS, and then Memory 5a and other memos +75 b
Similarly, the data can be accessed via the MPXs 4a to 4d.Also, the data is sent from the memories 5a and 5b to the CPtJO via the input 4PX4e. It is not necessary to implement the register i2b.Since the embodiment of the present invention is configured as described above, the Marusen system uses two independent storage devices, such as CPU0 vs. memory 5a and CPUI vs. memory 5b. In the synchronized system, memory 5a + memory IJ is used for CPUo.
5b can be operated as a storage device. The above description has been made using a divided storage unit and controlling 5EL3 and 4a-e of 2 groups using a 1-bit selection signal, but if necessary, the storage device ζ having a basic configuration of 2n may be used to control the order bits. By 2°! This can be realized by combining an arbitrary number of divided storage sections with a single CPU or an arbitrary number of CPUs, and the device unit can be a printed wiring board unit C, a rack unit, a DRAM, or other static random access memory (SkC). Needless to say, the same can be applied to 8M.

+g+ As described in the detailed description of the invention, according to the present invention, the maximum storage capacity of the storage device is controlled by one or more central processing units (CPUs).
This is for M because a common implementation format provides a combination of divided storage sections that provides an arbitrary maximum storage capacity that is compatible with the storage capacity required for the.

[Brief explanation of drawings]

The figure shows a block diagram of a storage device control system in one embodiment of the present invention. In the figure, la and lb are memory access control units, 2a and 2b are address registers, 3 is an output selector (e3EL bar 4a-e are large blade selectors (MPX), and 5a and b are divided storage units.

Claims (1)

[Claims] Some storage devices are equipped with a plurality of divided storage sections, a plurality of access control means corresponding to each divided storage section, and a means for selecting each divided storage section according to a selection signal placed above an address signal. When operating the °C memory device corresponding to a plurality of central processing units configured and connected to the outside, each control means resets the selected selection means to 0 according to the address signal 9 without a selection signal. In order to support a smaller number of central processing units, the corresponding divided memory sections are accessed independently and separately, and the upper control means among the plurality of control means is selected by the selection means from the plurality of divided memory sections under control. Signal IC
Accordingly, a storage device control method is characterized in that a divided storage section is selected to access a part or all of the storage capacity of the storage device.