JPS62231364A - Electronic equipment - Google Patents

Abstract

PURPOSE:To set an I/O address in an address space with a simplified constitution, by providing a logic circuit that outputs a signal which controls the input/ output of data to a storage device, and an I/O to be connected to a peripheral equipment. CONSTITUTION:A CPU1 has address ports 50-59 which designate an address to store the data, and a read signal port 60 which reads the data, and is connected to a RAM2 and a ROM3 which have an output enable (OE) port 85 which enables the data to be outputted. Also, the CPU1 is connected to an I/O4 which is connected to a peripheral equipment 5, and having a chip selector CS86 which enables the data to be outputted. When the CPU1 designates a specific address, and accesses to the RAM2 or the ROM3, only the storage device whose address is designated, is enabled to operate, and another storage device and the I/O4 are disabled to operate, by an inversion circuit 9, and OR circuits 6 and 8. When the I/O4 is accessed, the input of the data is diabled at the I/O4 and the operations of the RAM2 and the ROM3 are disabled, by the circuit 8 and the CS86.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to electronic devices such as computers and printers that have a memory and exchange data with peripheral devices.

BACKGROUND OF THE INVENTION In recent years, electronic devices such as computers have become widespread, and some have large storage capacities and others have many peripheral devices connected to them.

Generally, electronic devices are equipped with a central processing unit (hereinafter referred to as C
It is abbreviated as PU. ) and read-only memory (hereinafter abbreviated as ROM) that stores programs and data.
and a random access memory for storing data at any time, and an input/output port (hereinafter abbreviated as Ilo) connected to peripheral devices.

The ROM will be explained below using FIG. As shown in FIG. 3(C), the address *30. Data line 31, chip enable (hereinafter referred to as CE) for activating the ROM 29; signal line 32, output enable (hereinafter referred to as OE) for enabling output.
It is abbreviated as. ) There is a signal line 33, and when reading data from the ROM 29, as shown in FIG. It is necessary to input a signal to To do this, first see Figure 3 (
As shown in FIG. 3(a), the CE signal line 32 is connected to the ground and kept in a valid state at all times, and the OE signal line 33 is controlled to read data, or as shown in FIG.
There are those that connect the signal line 33 to the ground and control the GE signal line 32 to read data, and those that connect the OE signal line 33 and C
There was one that simultaneously controlled the E signal line 32 and extracted data.

Generally, the storage capacity of a ROM is configured to be 2 to the Nth power bits, where N is the number of address signal lines.

When an electronic device is provided with an Ilo for communicating with peripheral devices in addition to the ROM described above, the Ilo address needs to be assigned to an address different from the ROM address.

Problems to be Solved by the Invention However, in the conventional configuration described above, when attempting to connect Ilo, the number of address lines increases, and the problem is that a central processing unit that can support a wide address space must be used. It had

If you try to connect Ilo without using a central processing unit that can port a wide address space, the ROM
Since the capacity of is made discretely, it is necessary to increase the number of ROMs to create an address space excluding the address corresponding to Ilo, but in this case, the problem is that the number of ROMs increases and the cost increases. It had

Means for Solving the Problems The present invention provides a system that prevents the output of data to the CE port of the memory when the central processing unit connected to the address port and the read signal port designates a specific address and attempts to read data. It is equipped with a logic circuit that outputs a signal that enables the output of data = 3- to the chip selector of Ilo.

Effect: With the above configuration, the address of Ilo can be provided in the address space without increasing the address space of the central processing unit (and without increasing the number of memories).

Embodiment FIG. 1 is a circuit diagram of an electronic device according to an embodiment of the present invention. In the figure, 1 is a CPU that performs calculations, and the CPU
1 has address ports 5o to 59, data ports 70.
It has a read signal port 60 and a write signal port 61. 2 has a CE port 81, an OE port 82, and a WE port to enable writing, and a RAM 13 connected to address ports 50 to 59 and a data port 70 by signal lines is connected to the address port 50 via an inverting circuit 9.
A ROM 4 has a CE port 84 and an ○E port 85 connected to the address ports 50 to 59 and a data port 70, and a chip selector 4 (hereinafter abbreviated as C8) that enables data input. ) and connected to a peripheral device ■10.5 is a peripheral device connected to Ilo, 6
is connected to the address port 50 via the inverting circuit 9,
Further, the OR circuit 7 connected to the address ports 51 to 57 is an AND circuit to which the output of the OR circuit 6 and the state of the read signal port 60 are inputted via the inverting circuit 10. The output is connected to OE port 85. 8 is the output of the OR circuit 6 and the read signal port 6
This is a logical sum circuit to which the state of 0 is input, and the logical sum circuit 8
The output of is connected to C886.

Next, the memory space accessed by the CPUI will be explained.

As shown in FIG. 2(a), the memory space 80 includes RAM.
, 81 are assigned Ilo, and 82 is assigned a ROM.

Regarding the electronic device of this embodiment configured as above,
The operation will be explained below.

First, when the CPUI accesses the RAM 2, the address of the memory space 80 is designated. At this time, the address port 50 is O[V] (hereinafter abbreviated as L level).
Then, a chip enable signal is input to the CE port 81 of the RAM 2, and the RAM 2 becomes accessible.

Next, the CPUI outputs a signal to the OE port 82 or the WE port 83 to read and write data.

At this time, the state of the address port 50 is inverted by the inversion circuit 9, the CE port 84 becomes +5 [■] (hereinafter abbreviated as H level), and the ROM 3 does not operate. Further, an H level signal is input to the OR circuit 6 from the address port 50 via the inverting circuit 9, and its output is input as an H level signal to the CS port via the OR circuit 8, so l104 is the data. is not output.

When accessing Ilo next, when the address shown in the table of FIG. 2(b) is specified, the output of the OR circuit 6 goes to L level, the CE port 84 of ROM3 goes to H level, and ROM3 becomes inoperable. becomes possible. Further, the CS port 86 of l104 becomes L level, allowing input of data from peripheral devices.

Next, when the CPUI accesses ROM3, the CPU
specifies an address, outputs a signal to the read signal port 60, and reads data. At this time, since the address port 50 is at H level as shown in the table of FIG. 1104 does not output data because it is at the H level due to 1 and 8.

Effects of the Invention The present invention is connected to an address port and a read signal port, and when the central processing unit specifies a specific address and attempts to read data, it becomes impossible to output data to the CE port of the memory. It is equipped with a logic circuit that outputs a signal that enables output of data to the chip selector of Ilo, and has an Ilo in the address space of the memory.
Since an address corresponding to lo can be provided, I
Even if a new lo is provided, there is no need to use a CPU that can port a wide address space, and the number of memories does not increase.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an electronic device in an embodiment of the present invention,
Figure 2 (a) is the memory map, Figure 2 (b) is a table showing the address port status when each memory or Ilo is selected, Figure 3 (a), Figure 3 (b), Figure 3(c) is a plan view showing the usage state of ROM, Figure 4 is RO
It is a timing chart when M is used. 1.CPU, 3.ROM. 4...l101 6.8...OR circuit,
7...AND circuit, 9.1o...Inversion circuit, 50-59...Address port, 60...Read signal port, 85...OE port,
86...Name of CE Port agent Patent attorney Toshio Nakao and 1 other person rumored -1-1 : → : : Hitsugi ni 1 Xi ) Figure 2 (wide) (b)

Claims (1)

[Claims] A central processing unit that performs calculations and has multiple address ports that specify data storage addresses and a read signal port that requests data reading, and an output enable port that enables data output and stores data. an input/output port that is connected to a peripheral device and has a chip selector that enables data output; and an input/output port that is connected to the address port and the read signal port, and that is connected to the a logic circuit that specifies an address and outputs a signal to the read signal port, outputs a signal disabling data output to the output enable port, and outputs a signal enabling data output to the chip selector; An electronic device characterized by: