JPH01149445A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the dispersion of a signal transmission path length reaching from an input node to an output node through each functional block and to form the length into the shortest length as a whole by a method wherein the functional blocks are arranged in such a way that the sums of the signal conductor lengths ranging from the respective functional blocks to the input node and the signal conductor lengths ranging from the respective functional blocks to the output node become an almost same length. CONSTITUTION:An input buffer IB and an output buffer OB are respectively arranged on both sides of memory mats MM0-MM5 holding the memory mats MM0-MM5 between them and an internal address signal and an internal readout signal are considered so as to be moved on a semiconductor substrate along their logical flows. Moreover, the memory mats are designed in such a way that the sums of the distances ranging from the output terminal for the internal address signal of the butter IB, which is used as an input node, to the memory mats, that is, the input signal conductor lengths, and the distances ranging from the output terminals of the memory mats to the input terminal of a tag comparison circuit TC, which is used as an output node, that is, the output signal conductor lengths, become an almost same length in all the memory mats. Thereby, the variability of the signal transmission path length reaching from the buffer IB to the buffer OB through each memory mat is made least and the length is formed into the shortest length as a whole.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a semiconductor integrated circuit device,
For example, the present invention relates to a technique that is particularly effective when used in a tag memory included in an address translation buffer of a computer system employing a virtual memory method.

[Conventional technology]

Virtual storage is one way to overcome the constraints imposed by the physical properties of storage devices and create flexible program systems. A computer system using this virtual storage method is provided with an address conversion buffer for converting a logical address output from a processing device into a physical address on a storage device within the bus cycle.

The address translation buffer includes two memories to which respective addresses are associated, namely a tag memory and a frame memory. Compare and match with the tag stored in . As a result, if both data match, the frame number stored at the corresponding address in the frame memory is read out and made part of the physical address.

The address conversion buffer is described, for example, in "Nikkei Electronics J," published by Nikkei McGraw-Hill, December 5, 1983, pages 137 to 152.

[Problem that the invention seeks to solve]

Prior to the present invention, the inventors of the present application considered using a memory with logical functions having a plurality of memory mats as the tag memory of the address translation buffer. In these memories with logic functions, each memory mantle and logic circuit have a basic configuration of bipolar transistors. The logic circuit constitutes a tag comparison circuit for comparing and verifying the given search data and the tag read from each memory mat. The address conversion buffer repeatedly accesses the memory with logical functions while sequentially changing the address, and when the search data and the read tag match,
Loads read data from a separately provided frame memory.

However, the inventors of the present invention have discovered that the above memory with logical functions has the following problems. That is, as described above, the memory with logical functions includes a plurality of memory mats. The pads for inputting and outputting address signals and storage data to and from these memory mats are arranged on the semiconductor substrate on which the memory with logic function is formed, so as to be compatible with, for example, conventional logic #B simple memory. Ru. Therefore, the distance from each pad to each memory mant, that is, the length of the signal line for transmitting address signals and read data, exhibits relatively large variations, and the transmission delay time of each signal varies from memory mat to memory mat. This is due to the fact that as memory with logic functions becomes larger in capacity and its semiconductor substrate becomes larger,
Expanding the variation in access time of each memory mat,
As a result, the access time and cycle time of the memory with logic functions are slowed down. For this reason, the time required for address translation in the address translation buffer increases, and the processing capacity of the entire computer system including the address translation buffer decreases.

An object of the present invention is to reduce variations in signal transmission time in a memory with logic functions, etc., including a plurality of functional blocks. Another object of the present invention is to speed up the access time and cycle time of a memory with logical functions, etc., and improve the processing capacity of a system including the same.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, input nodes and output nodes that respectively transmit input signals and output signals to multiple functional blocks such as memory mats are arranged on both sides of the functional blocks, and from each functional block to the input nodes and output nodes. The arrangement is such that the sum of the signal line lengths, that is, the signal transmission path length for each functional block, is approximately the same length for all functional blocks.

[For production]

According to the above-described means, variations in signal transmission time from an input node to an output node via each functional block are reduced, and as a result, the access time and cycle of a memory with logic function, etc. including these functional blocks is reduced. Since the time can be sped up, the processing capacity of a system including a memory with logical functions can be improved.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of an address translation buffer TLB including a memory with logic functions to which the present invention is applied.

Although not particularly limited, the address translation buffer TLB of this embodiment is included in the memory management unit, and is included in the processing device C.
Logical address LA output from PU is converted to physical address P
It has the function of converting into A and transmitting it to the main storage device MS, etc.
The logical address LA includes, but is not particularly limited to, an index part ID and an offset part O3.Of these, the offset part O8 is transmitted as is as part of the physical address PA, and the index part ID is transferred to this address translation buffer TLB. After being converted into a frame number FN by , it becomes the remaining part of the physical address PA.

The address translation buffer TLB of this embodiment includes a tag memory TM whose basic configuration is a memory with a logical function to which the present invention is applied, and a frame number memory FNM whose basic configuration is a similar memory without a logical function. These tag memory TM and frame number memory FNM each have the same number of associated addresses. That is,
A tag corresponding to the index part ID of the logical address LA is stored in each address of the tag memory TM, and a tag corresponding to the index part ID of the logical address LA is stored in each address of the tag memory TM.
A frame number FN corresponding to the tag stored in the corresponding address is stored. The addresses of the tag memory TM and the frame number memory FNM are arbitrarily assigned at any time when a miss occurs in the tag memory TM.

The address translation buffer TLB further includes an address translation buffer control circuit TLBC. The address translation buffer control circuit TLBC controls the tag memory TM and frame number memory FNM, and controls the address translation buffer TL.
Controls the entire operation of B. Address translation buffer control circuit TLBC, tag memory TM and frame number memory F
The address translation buffer TLB including NM is configured by a plurality of semiconductor integrated circuit devices mounted on one mounting board, although not particularly limited thereto.

In FIG. 2, the logical address LA output from the processing device CPU includes an offset section O8 and an index section ID.
As described above, the offset section O8 is transmitted as is to the main storage device MS as part of the physical address PA, and the index section ID is supplied to the address translation buffer TLB.

The address translation buffer TLB is brought into operation by an activation control signal (not shown), and the tag memory TM starts comparing and collating the index section ID, that is, the tag. That is, the address translation buffer TLB uses the index section ID of the m+l bit supplied from the processing device CPU as the search data IDO to IDm to the tag memory T.
Supply to M. At the same time, the address signals AO to AI of l+1 bits are supplied to the tag memory TM and the frame number memory FNM while being changed in a predetermined order. As a result, the tag stored in the designated address of the tag memory TM is read out and compared and verified by the logic section of the tag memory TM. Further, in the frame number memory FNM, a reading operation of the frame number FN stored at the corresponding address is started.

Here, the tag memory TM is constituted by a memory with logical functions, as described above, and similarly includes a frame number memory FN, which includes six memory mantles, although it is not particularly limited.
M includes six memory mants provided corresponding to each memory mat of the tag memory TM. Therefore, the tag comparison and verification operation in the tag memory TM is performed simultaneously for six memory mats, and the results are outputted as tag match signals TMO to TM5 to the address translation buffer control circuit TLBC. These tag match signals TMO~
TM5 includes the tag read from the specified address of the corresponding memory mat and the search data IDO to IDm supplied from the address translation buffer control circuit TLBC.
When all bits match, the signal is selectively set to high level. When any of the tag match signals TMO-TM5 is set to a high level, the address translation buffer control circuit TLBC sets the corresponding read selection signals R3O to R35 to a high level, although not particularly limited, and converts the frame number memory FNM to a high level. The frame number FN read from the corresponding memory mat is read data RFO to RFn.
Selectively import as . These read data R
FO to RFn are transmitted to the main storage device MS as part of the physical address PA, that is, as the frame number FN.

By the way, when the tag memory TM has a mishit and a tag that matches the given search data IDO to IDm is not stored in the tag memory TM, the address translation buffer control circuit TLBC first converts the DAT controller (not shown), although not particularly limited thereto, into the tag memory TM. Start. This allows D.A.
The T controller accesses the address translation table provided in the main memory device MS, reads out the frame number FNt-corresponding to the index section ID, and sends it to the address translation buffer TLB. The address translation buffer TLB converts the index section ID and the frame number FN supplied from the DAT controller into the write data WDO~
It is supplied to the tag memory TM and frame number memory FNM as WDm and WFO to WFn. Further, according to a predetermined algorithm, addresses with a low probability of being accessed in the future in the tag memory TM and frame number memory FNM are selected, and the tag memory TM and frame number memory are used as write selection signals WSO to WS5 and address signals AO to Ai. Supply to FNM.

As a result, tag memory TM and frame number memory F
The index part ID related to the mishit logical address LA and the corresponding frame number FN are written to the corresponding address of the memory mantle corresponding to NM.

FIG. 1 shows a block diagram of an embodiment of the tag memory TM of the address translation buffer TLB of FIG. 2. In FIG.

The circuit elements constituting each block in the figure are formed on a single semiconductor substrate such as, but not limited to, single crystal silicon. In the figure, each block constituting the tag memory TM is written at a position τ that approximately corresponds to the actual arrangement position on the semiconductor substrate.

In FIG. 1, the tag memory TM is composed of six memory mats MMO to 6, which are functional blocks, although not particularly limited thereto.
These memory mats, including MM5, are tag memory T
It is arranged in a relatively large area approximately in the center of the semiconductor substrate where M is formed. The tag memory TM further includes a logic section having a basic configuration of a logic gate circuit composed of bipolar transistors, that is, an input buffer IB and an output buffer OB.

It includes a tag comparison circuit TC and a data selection circuit DSL. Among these, the input pants-tlB is arranged on one side of the semiconductor substrate on which the tag memory TM is formed, and the output buffer OB
The tag comparison circuit TC and the data selection circuit DSL are arranged on the opposite side of the semiconductor substrate across the memory mantle.

Address signals AO to Ai and search data IDO to I supplied from the address translation buffer control circuit TLBC
Dm, write data WDO to WDm.

The write selection signals WSO to WS5 and the read selection signals R5O to R35 are first input to the input buffer IB,
Retained. Of these, address signals AO to Ai and write data WDO to W D m are commonly supplied to memory mants MMO to MMS as internal address signals aQxai and internal write signals wdQ to wdm. Further, the write selection signals WSO to WSS are applied to the corresponding memory mats MM as internal write selection signals wsO to ws5.
O to M M5 are respectively supplied. Furthermore, the search data IDO-IDm is the internal search data ldO-idm.
is supplied to one input terminal of the tag comparison circuit TC as
The read selection signals R3O to R35 are supplied to the data selection circuit DSL as an internal read selection signal rsO''rs5.

Although memory mats MMO to MM5 are not particularly limited,
Each includes a memory array and peripheral circuits such as an address decoder and a sense amplifier. Among these, the memory array is
The memory array and peripheral circuitry include a word line with a multiplication factor of 2 (i+1), m+1 sets of complementary data lines, and a plurality of memory cells arranged in a lattice at the intersections of these word lines and complementary data lines, as described above. Like the input buffer IB, etc., the basic configuration is a memory cell made of a bipolar transistor and an 8-remain gate circuit.

Memory mats MMO to MM5 are the above-mentioned cover sofa IB.
According to internal address signals aQ to ai supplied from
One corresponding word line is brought into a selected state. As a result, the storage data, ie, the tag, stored in the m+1 memory cells coupled to the selected word line is read. These tags are connected to each memory mantle's read signal rd.
The signals oO to rdQm to rd5ONrd5m are supplied to the corresponding input terminals of the tag comparison circuit TC, and are also supplied to the corresponding data input terminals of the data selection circuit DSL. When a word line is selectively selected,
When the internal write selection signals WsO to ws5 are alternatively set to high level, the corresponding memory mats MMO to M
M5 is put into a write operation state and writes the tag, or internal write signals wdQ to wdm, into m+1 memory cells coupled to the selected word line.

Although not particularly limited, the tag comparison circuit TC includes six unit comparison circuits provided corresponding to the memory mats MMO to MM5, and one input terminal of each unit comparison circuit receives the internal search data idO to idm is commonly supplied, and the other input terminal receives the internal read signals rd00 to rd5 from the corresponding memory mat.
0 to rd5m are supplied respectively.

Each unit comparison circuit of the tag comparison circuit TC receives the internal readout signal r corresponding to the internal search data ido to idm.
d 00 to rd Om to rd50 to rd5m are compared and verified bit by bit. As a result, when all bits of both data match, the output signal, that is, the internal tag match signal tmo to tm5 is selectively set to high level. These internal tag match signals tmo~tm5
is supplied to the output buffer OB, and further supplied to the address translation buffer control circuit TLBC as a tag match signal 1'MO-TM5.

The data selection circuit DSL selects the internal read signals rdOO=rdQm to rd50 to rd5m supplied from each memory mat according to the internal read selection signals rsO to rs5, and selects the internal read signals rdO to rdm. This will be communicated to the outgoing sofa OB as follows.

These internal read data rdO-rdm are further supplied to the address translation buffer control circuit TLBC as read data RDO-RDm. Note that the read operation of the tag memory TM is executed only during a predetermined test operation of the address translation buffer TLB.

By the way, when the address translation operation by the address translation buffer TLB is performed, the tag memory TM receives the address signal A O"A i from the address translation buffer control circuit TLBC corresponding to the index part ID of the logical address LA, as described above. Search data IDO=I
Dru is supplied. Memory mats MMO to MM5 of the tag memory TM are activated simultaneously by address signals AO to AI, and the tags stored at specified addresses, that is, internal read signals rdoo''rdom to rd.
50 to rd5m are output to the tag comparison circuit TC. These internal read signals are processed by the corresponding unit comparison circuit of the tag comparison circuit TC to read the search data! It is compared bit by bit with DO~IDm, and as a result, the tag match signal T
M O-TM 5 is selectively set to high level. In other words, the access time and cycle time of the tag memory TM depend on the access time of the memory mats MMO to MMS themselves, and at the same time, the time required for the input signal, that is, the internal address signal aOxal, to be transmitted to each memory mat. The signal transmission time and the output signal, that is, the internal read signal rdoO to rdOm to rd of each memory mat
It depends on the sum of the signal transmission time until 50 to rd5m are transmitted to the tag comparison circuit TC. Needless to say, these signal transmission times depend on the sum of the wiring lengths of the corresponding signal lines.

For these reasons, in the tag memory TM of this embodiment,
First, memory mat MMO-MM5 is made large enough that variations in signal transmission time within it do not pose a problem. In addition, input buffer IB and output cover sofa O
B is, as mentioned above, these memory mats MMO to M
They are arranged on both sides of M5, and care is taken so that the internal address signal and internal read signal move on the semiconductor substrate along their logical flow. Furthermore, when focusing on each memory mat, the distance from the output terminal of the internal address signal of the input cover sofa IH, which is an input node, to the memory mat, that is, the input signal line length, and the output terminal of each memory mat, which is an output node. The distance to the input terminal of the tag comparison circuit TC, ie, the sum of the length of the output signal line, is designed to be approximately the same length for all memory cloaks. Therefore, variations in the length of the signal transmission path from input buffer IB to output buffer OB via each memory mat are minimized and overall shortest. This equivalently shortens the critical path of the tag memory TM and speeds up its access time and cycle time.

As described above, the address translation buffer TL of this embodiment
The tag memory TM of B has a basic configuration of a plurality of memory mats MMO to MM5 divided to such an extent that variations in signal transmission time within the tag memory TM do not become a problem. Input signals such as address signals are supplied to these memory mats via input buffers IB. In addition, the output signal of each memory mant is converted into search data I by the tag comparison circuit TC.
It is compared with DO~IDm, and as a result, tag match signals TMO~TM5 are sent out via the output buffer OB. Memory mats MMO to MM5 are arranged approximately at the center of the semiconductor substrate on which the tag memory TM is formed, and an input buffer IB, a tag comparison circuit TC, and an output buffer OB are arranged, respectively, across these memory mats. .

Furthermore, each The length of the signal transmission path between the input node and the output node of the memory mat is designed so that the variation thereof is minimized and the overall length is the shortest. For these reasons, in the tag memory TM of this embodiment, the critical path is equivalently shortened, and the access time and cycle time are increased. As a result, the address translation buffer T containing the tag memory TM
The address translation operation of the LB is sped up, and the processing capacity of the combiator system including the address translation buffer TLB is improved.

As shown in the above embodiment, when the present invention is applied to the tag memory 7M included in the address translation buffer of a combiator system employing a virtual memory method, the following effects can be obtained. In other words, (11) Input nodes and output nodes that respectively transmit input signals and output signals to multiple functional blocks such as memory mats are placed on both sides of the functional block, and the input nodes are transmitted from each functional block to the input node. By arranging the signal lines so that the sum of the signal line lengths from the input node to the output node are approximately the same, variations in the length of the signal transmission path from the input node to the output node via each functional block can be reduced, and the overall length can be reduced. This has the effect of making it the shortest length possible.

(2) According to the above item (11), it is possible to shorten the critical path of a memory with logical functions including a plurality of functional blocks, and to speed up its access time and cycle time.

(3) With the above items (1) and (2), it is possible to speed up the address translation operation of the address translation buffer that uses memory with logical functions as tag memory, and increase the processing capacity of a computer system that uses a virtual memory method. This effect can be obtained.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without getting the gist of the invention. For example, in the embodiment shown in FIG. The IB may be arranged in the center of the semiconductor substrate, and the memory mat and the output bumper OB may be arranged outside the IB so as to surround the input bumper IB. Iruka Sofa IB, Deba Buffer OB and Memory Cloak MMO~M
Various embodiments can be considered for the method of arranging M5 and the like, provided that the logical flow of each signal and the actual movement direction of each signal on the semiconductor substrate substantially match. The signal transmission path seen from the input node and the output node is, for example, an appropriate i! By adding an extension circuit, etc., the length may be equivalently the same.Also, the memory mant may be divided into a number other than six, and the memory mant may have functions other than the memory mat. It can also be replaced with blocks. Each block of the tag memory TM may have a basic configuration of, for example, a logic gate circuit or memory cell consisting of a complementary MOS. In the embodiment shown in FIG.
The IJFNM and frame # may be formed on a common semiconductor substrate, or the entire address translation bumper TLB may be formed on one semiconductor substrate. Furthermore, various embodiments may be adopted, such as the block configuration of the tag memory TM shown in FIG. 1, the block configuration of the address translation buffer TLB shown in FIG. 2, and combinations of address signals and control signals.

In the above explanation, the invention made by the present inventor was mainly applied to the tag memory of an address translation buffer, which is the background field of application, but the invention is not limited to this, and for example, cache memory, etc. The present invention can also be applied to bipolar memory used alone as a memory, and other digital integrated circuits including a plurality of functional blocks. The present invention can be widely applied to semiconductor integrated circuit devices including output nodes and output nodes.

[Results of invention]

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, input nodes and output nodes that respectively transmit input signals and output signals to a plurality of functional blocks such as a memory mantle are placed on both sides of the functional block, and the input nodes and output nodes are transmitted from each functional block to the input node and the output node. By arranging the signal lines so that the sum of the signal line lengths to the nodes are approximately the same, variations in the signal transmission path length from the input node to the output node via each functional block are reduced, and the overall length is reduced. Since it can be made to the shortest length, it can speed up the access time and cycle time of memory with logical functions including multiple functional blocks,
It is possible to speed up the operation of an address translation buffer or the like using a memory with logical functions as a tag memory, thereby increasing the processing capacity of a computer system or the like that includes the address translation buffer or the like.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing an embodiment of a tag memory of an address translation buffer to which the present invention is applied, and FIG. 2 is a block diagram of an address translation buffer including the tag memory of FIG. 1. FIG. 2 is a block diagram showing one embodiment. TM...Tag memory, MMO to MM5...Memory mat, IB...Input buffer, OB...Output buffer, TC...Tag comparison circuit, DSL...Data selection circuit. TLB: address translation buffer, TLBC: address translation buffer control circuit, FNM: frame number memory, CPU: central processing unit, MS: main memory.

Claims (1)

[Claims] 1. An input node to which a predetermined input signal is transmitted; a plurality of functional blocks that receive the input signal and perform predetermined operations;
an output node to which an output signal of the functional block is transmitted, and the input node and a plurality of functional blocks and output nodes, and signal lines provided between these are connected from each of the functional blocks to the input node and the output node. A semiconductor integrated circuit device characterized in that the semiconductor integrated circuit device is arranged so that the sum of distances to nodes are substantially the same length. 2. The input node and the output node are arranged on both sides of the plurality of functional blocks, and the signal lines are arranged so that the corresponding signals move on the semiconductor substrate along their respective logical flows. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is arranged in a semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein each of the functional blocks has a size such that variation in signal transmission time within the functional block does not pose a problem. 4. Claims characterized in that the functional block is a memory mat including a memory array and its peripheral circuit, and the semiconductor integrated circuit device is a memory with a logic function including the plurality of memory mats. The semiconductor integrated circuit device according to item 1, item 2, or item 3. 5. The semiconductor integrated circuit device according to claim 1, 2, 3, or 4, wherein the memory with logic function is a tag memory included in an address conversion buffer. 6. The input signal is an address signal, and the output signal is a read signal for the memory mat. Claims 1, 2, 3, and 4. Or the semiconductor integrated circuit device according to item 5.