JPS59188135A - Attracting method of semiconductor substrate - Google Patents
Attracting method of semiconductor substrateInfo
- Publication number
- JPS59188135A JPS59188135A JP6089983A JP6089983A JPS59188135A JP S59188135 A JPS59188135 A JP S59188135A JP 6089983 A JP6089983 A JP 6089983A JP 6089983 A JP6089983 A JP 6089983A JP S59188135 A JPS59188135 A JP S59188135A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- plates
- semiconductor substrate
- voltage
- attracting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67109—Apparatus for thermal treatment mainly by convection
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/50—Substrate holders
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
- H01L21/6833—Details of electrostatic chucks
Abstract
Description
【発明の詳細な説明】 (イ)発明の技術分野 木兄り」は半導体基板の吸着方法に関する。[Detailed description of the invention] (b) Technical field of the invention ``Kienori'' relates to a method for adsorbing semiconductor substrates.
(ロ)従来技術と問題点
半導体装飯の製造プロセスでは半導体基板を処理装置内
に固定する必要が生ずる。従来、真空79着法が用いら
れているが、減圧下で処理する場合に吸着力が弱くなり
王道1当である。そこで、そうした不都合のない静M1
吸着法も利用されるが、次の様々問題がある。(B) Prior Art and Problems In the manufacturing process of semiconductor devices, it is necessary to fix the semiconductor substrate within the processing equipment. Conventionally, a vacuum 79 bonding method has been used, but when processing under reduced pressure, the suction force becomes weaker, so it is the standard method. Therefore, static M1 without such inconvenience
Adsorption methods are also used, but they have the following problems.
第1図は静π(、吸着法を説明する模式図である第1図
(イ)の態様では、平面i、tiII!l上に形成され
た絶縁性薄膜2の上に、半導体基板3を載置し、電極l
と半導体基板3の間に電圧を印加することによって基板
3を吸着している。第1図(ロ)の態様では、対をなす
平面電極4,5の上に絶縁性薄膜2を形成し、その上に
半導体基板3を載置して電極4.5間に電圧を印加する
ことによって吸着している。かかる静電吸着法において
吸着力を高めるためには、絶縁膜の厚さを薄くするか印
加電圧を上げる必要がある。しかし、この2つの方法は
相反するところがある。すなわち、絶縁破壊を防ぐため
に、絶縁膜をうずくすると印加電圧を下け々けれは々ら
ず、逆に印加電圧を上げると絶縁膜を厚く形成しなけれ
ばならないからである。更に、絶縁膜は樹脂で作成され
るので、熱伝導性が悪く、そのために半導体基板の冷却
が困難である。。In the embodiment of FIG. 1 (A), a semiconductor substrate 3 is placed on an insulating thin film 2 formed on a plane i, tiII!l. Place the electrode l
By applying a voltage between the semiconductor substrate 3 and the semiconductor substrate 3, the substrate 3 is attracted. In the embodiment shown in FIG. 1(b), an insulating thin film 2 is formed on a pair of planar electrodes 4 and 5, a semiconductor substrate 3 is placed on top of the insulating thin film 2, and a voltage is applied between the electrodes 4 and 5. It is absorbed by this. In order to increase the adsorption force in such an electrostatic adsorption method, it is necessary to reduce the thickness of the insulating film or increase the applied voltage. However, these two methods are contradictory. That is, in order to prevent dielectric breakdown, if the insulating film is warped, the applied voltage must be lowered considerably; on the other hand, if the applied voltage is increased, the insulating film must be made thicker. Furthermore, since the insulating film is made of resin, it has poor thermal conductivity, making it difficult to cool the semiconductor substrate. .
e→ 発明の目的
本発明は、以上の如き従来技術の現状に鑑み、半導体基
板を容易かつ強力に吸着し、しかも凛JJ+効率の良い
吸着方法を提供することを目的とする。e→ Purpose of the Invention In view of the current state of the prior art as described above, it is an object of the present invention to provide a method for easily and strongly adsorbing a semiconductor substrate and also having high efficiency.
に)発、明の構成
干して、上記目的を達成する本発明は、牛梼体ノ3(板
を少なくとも1個の平面■1極上に直接に載置し、該平
面箱、極と該半導体基板の間に電圧を印加して、ジョン
セン・ラーペク効牙2により該半導体基板を該平面電極
に吸着するととを特徴とする半導体基板の吸着方法にあ
る。The present invention achieves the above object by placing a plate directly on at least one flat surface and connecting the flat box, the pole and the semiconductor. A method for adsorbing a semiconductor substrate is characterized in that a voltage is applied between the substrates and the semiconductor substrate is adsorbed to the flat electrode by a Johnsen-Rapek effect 2.
(ホ)発明の実施例
本発明で利用するジョンセン・ラーベク(Johnse
n−Rahbek )効果とは、半導体と金属または半
導体と半導体を面で接触させ、200V程度の電圧を印
加するとそれらの間に吸着力が働く現像をいう。半導体
を金属まだは半導体に面で接触させると、微視的には両
者は僅小々点で接触し、10−′〜1O−7crn程度
の小間隙をもつ平行平板コンデンサの両電極と等価な状
態になシ、吸着力を生ずるのである。この吸着力Fを式
で表わすとε=εrε
式中、ε:小間隙の誘電宗
■:印加得7圧
d:小間隙の大きさ
S:接触面積
εr:1〜lO
εo : 8.9X I O”[IC2N’ m″″2
〕である。単位面積当りの吸オ′fカを試算するために
ε、=1.εo ”= 8.9 X 10−”[C2N
−’cm ”]、 V=200〔v〕、d=lO−7
〔m〕、S−10−4〔m2〕を代入すると、F =
1.78X] 03[N]= 1.74 X ] O’
Kg重である。実際にはこの1%程度の吸着力が発生す
るが、それでも吸着力は大きい(静電、吸着の約100
倍)。しかも、半導体基板を金属または半導体に直接接
触させて置くので半導体基板の冷却効率もよくなる。(e) Embodiments of the invention
The n-Rahbek) effect refers to a development in which when a semiconductor and a metal or a semiconductor and a semiconductor are brought into surface contact and a voltage of about 200 V is applied, an adsorption force acts between them. When a semiconductor is brought into surface contact with a metal semiconductor, microscopically they contact each other at a very small point, which is equivalent to the electrodes of a parallel plate capacitor with a small gap of about 10-' to 1O-7 crn. In this state, an adsorption force is generated. This adsorption force F is expressed by the formula ε=εrε In the formula, ε: dielectric strength of the small gap ■: applied pressure d: size of the small gap S: contact area εr: 1 to lO εo: 8.9X I O"[IC2N'm""2
]. In order to estimate the suction force per unit area, ε,=1. εo”=8.9×10−”[C2N
-'cm''], V=200 [v], d=lO-7
By substituting [m] and S-10-4 [m2], F =
1.78X] 03[N]= 1.74X] O'
It weighs Kg. In reality, about 1% of this adsorption force is generated, but the adsorption force is still large (approximately 100% of that of electrostatic and adsorption).
times). Moreover, since the semiconductor substrate is placed in direct contact with the metal or semiconductor, the cooling efficiency of the semiconductor substrate is improved.
半導体基板と平面電極の間に電圧を印加する方法は、第
2図(イ)に示す如く、平面電極6の上に半導体基板を
載置し、一方は平面電極6にそして他方は半導体基板2
の上から印加してもよいが、第2図(ロ)に示す如く、
相互に@置された対の平面型41i7.8上に半導体基
板2を載宿し、その対の平面電極7,8の間に電圧を印
加することKよってもよい。The method of applying a voltage between the semiconductor substrate and the planar electrode is as shown in FIG.
It may be applied from above, but as shown in Figure 2 (b),
It is also possible to place the semiconductor substrate 2 on a pair of planar molds 41i7.8 that are placed on each other, and to apply a voltage between the pair of planar electrodes 7 and 8.
第3図は本発明の具体的な1¥施例であるプラズマエツ
チング装置を概略的に示す。気密にした処理v]0はガ
ス清入口11およびガス排出口12を有し、ガス排出口
】2にはパルプ13を介して排気ポンプ14が接続され
、処理室10内は減圧にされる。シリコンウェーハ等の
被処理基板15は、処理室10内の吸着板(平面電極)
16゜17の上に載置される。吸着板(平面電極)】6
゜17は、同一平面をなす平坦な上面を有しかつ相互間
は厳格に隔置された対をなす例えばP形シリコン十漕体
の個片である。相互に絶縁された吸着板16.17に霜
、源18から200〜400■程度の電圧を印加すると
、各吸着板16.17と半導体基板15の間にも電圧が
かかり、ジョンセン・ラーベク効果で、半導体基板15
が吸着板16.17に吸着される。FIG. 3 schematically shows a plasma etching apparatus which is a specific embodiment of the present invention. The airtight processing v]0 has a gas inlet 11 and a gas outlet 12, and an exhaust pump 14 is connected to the gas outlet [2] via a pulp 13, so that the inside of the processing chamber 10 is reduced in pressure. A substrate 15 to be processed, such as a silicon wafer, is placed on a suction plate (plane electrode) in the processing chamber 10.
It is placed on top of 16°17. Adsorption plate (plane electrode)】6
17 are individual pieces of, for example, P-type silicon ten-column bodies, which form a pair having flat upper surfaces that are coplanar and are strictly spaced apart from each other. When a voltage of about 200 to 400 cm is applied from the frost source 18 to the suction plates 16 and 17 which are insulated from each other, a voltage is also applied between each suction plate 16 and the semiconductor substrate 15, resulting in the Johnsen-Rahbek effect. , semiconductor substrate 15
is attracted to the suction plates 16 and 17.
吸着板(平面電極)16,17娃、Al、O,宿の絶縁
板19を介して支持され、その支持体20には水冷の設
イ1i11が施されている。冷却水は冷却水入口22か
ら入り、支持体20の空洞21の中を循環し、冷却水出
口23から外へ出る。吸着板16゜17の上方には電極
24があり、高周波電源25から供給される電周波電力
の一方の電極をなしている。との高周波電力がガス導入
口から処理室内に導入されたガスをプラズマ化し、その
プラズマガスが半導体基板15をエツチングする。1プ
ラズマエツチング装置のその他の構成は慣用のものと同
材である。Adsorption plates (plane electrodes) 16 and 17 are supported via insulating plates 19 made of Al, O, and aluminum, and the support 20 is provided with water cooling equipment 1i11. Cooling water enters through the cooling water inlet 22, circulates within the cavity 21 of the support 20, and exits through the cooling water outlet 23. There is an electrode 24 above the adsorption plates 16 and 17, which serves as one electrode for the radio frequency power supplied from the high frequency power source 25. The high-frequency power of the plasma converts the gas introduced into the processing chamber from the gas inlet into plasma, and the plasma gas etches the semiconductor substrate 15. 1. The other components of the plasma etching apparatus are the same as conventional ones.
吸着板16.17は以上の実施例ではP型シリコン半導
体て作成したが、導電性ゴム、例えは、金属粉末入シの
硬質シリコーンゴム(抵抗値R≦300・副−3程度)
で作成すれは、ゴム弾性があるので、ゴミが吸着板表面
に41着しても半うy体基板と吸着板の密着性が阻けら
れること口ない。従って、安定した吸着力が得られ、吸
着ミスが防止される。更に、第4図に示す如く、導電性
ゴムの吸着表面に直径1 mm程度の多数の凸部をつく
il、ば、フミ伺唱のための吸着ミスがより確実に防止
される。尚、第4し1では、簡単のブζめ(で吸着板即
ち両’FUiw30 # 31を半円形で示し2だか、
実町、的には二重螺旋形力と効率の良いπ71極#j造
が用いられ、又ぞれが好寸しい。The adsorption plates 16 and 17 were made of P-type silicon semiconductor in the above embodiments, but they could also be made of conductive rubber, for example, hard silicone rubber containing metal powder (resistance R≦300, about -3).
Since the material made with this material has rubber elasticity, even if dust adheres to the surface of the suction plate, the adhesion between the semi-transparent substrate and the suction plate will not be hindered. Therefore, stable suction force can be obtained and suction errors can be prevented. Furthermore, as shown in FIG. 4, by providing a large number of convex portions each having a diameter of about 1 mm on the suction surface of the conductive rubber, suction errors due to filtration can be more reliably prevented. In addition, in the 4th and 1st, the suction plate, that is, both 'FUiw30 #31, is shown as a semicircle in 2 or 2.
In actual practice, a double helical force and efficient π71-pole #j structure are used, and each of them is well-sized.
(6)発りJ]の効果
以上の説明から明らかなように、本発明により、半居、
4A、;基板と電極の111に雀、圧を印加するだけで
その間に絶縁膜を設けるととなく半導体基板の強力な吸
着を実現することができる。従って、絶縁破壊の心配が
なく、シかも、強力で熱伝導性の良好な県庁゛1が可能
になる。不発り〕による装置d−構成か単純であり、製
造容易である。また、ゴミ伺着による吸着ミスを防止す
ることも可能である。(6) Effect of Departure J] As is clear from the above explanation, the present invention enables
4A; By simply applying pressure between the substrate and the electrode 111, strong adsorption of the semiconductor substrate can be achieved without providing an insulating film therebetween. Therefore, there is no need to worry about dielectric breakdown, and it is possible to construct a prefectural office building that is strong and has good thermal conductivity. The structure of the device is simple and easy to manufacture. Furthermore, it is also possible to prevent suction errors due to dirt adhering.
第1図は静電吸着法を説明する断面図、第2図1はジョ
ンセン・ラーペク効果を利用した吸光法を説明する断面
図、第3図は本発明の1実施例のプラズマエツチング装
俗の棚、略断面図、第4図は吸指板の1札様を示す斜視
図である1、
]、 、 4 、5 、6 、7 、8 ・・・平面電
極、2・・・絶縁膜、3・・・半導体基板、10・・・
処理室、16.17・・・吸着板(平面電極)、18・
・・tTt源、19・・・絶経体、24・・・電極、2
5・・・高周波電源、30.31・・・吸着板。
特許出願人
富士通株式会社
%許出願代理人
弁理士青水 朗
ブ1理士西舘和之
弁理士内田亭男
弁理士 山 口 昭 之
イf、 1 〜1
(イ) (
ロ)糸2 ’=+
(イ) (
ロ)第3図
慈41雫)FIG. 1 is a cross-sectional view explaining the electrostatic adsorption method, FIG. 2 1 is a cross-sectional view explaining the light absorption method using the Johnsen-Rapek effect, and FIG. 3 is a plasma etching device according to an embodiment of the present invention. Shelf, schematic sectional view, FIG. 4 is a perspective view showing one bill of the finger sucking board 1, ], 4, 5, 6, 7, 8... Planar electrode, 2... Insulating film, 3... semiconductor substrate, 10...
Processing chamber, 16.17...Adsorption plate (plane electrode), 18.
... tTt source, 19 ... Extinction body, 24 ... Electrode, 2
5... High frequency power supply, 30.31... Adsorption plate. Patent applicant: Fujitsu Limited Patent attorney: Akira Aomizu 1: Attorney: Kazuyuki Nishidate Patent attorney: Teio Uchida Patent attorney: Akira Yamaguchi
B) Thread 2'=+ (A) (
b) Figure 3 Ji 41 drops)
Claims (1)
載置し、該平■1電極と該半導体基板の間に電圧を印加
して、ジョンセン・ラーベク効果により該半導体基板を
該平面電極に吸着することを特a夕とする半導体基板の
吸着方法。1 Place a semiconductor substrate directly on at least one flat electrode, apply a voltage between the flat electrode and the semiconductor substrate, and place the semiconductor substrate on the flat electrode by the Johnsen-Rahbek effect. A method for adsorbing a semiconductor substrate, which is characterized in that it adsorbs to a semiconductor substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6089983A JPS59188135A (en) | 1983-04-08 | 1983-04-08 | Attracting method of semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6089983A JPS59188135A (en) | 1983-04-08 | 1983-04-08 | Attracting method of semiconductor substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59188135A true JPS59188135A (en) | 1984-10-25 |
JPH0531300B2 JPH0531300B2 (en) | 1993-05-12 |
Family
ID=13155661
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6089983A Granted JPS59188135A (en) | 1983-04-08 | 1983-04-08 | Attracting method of semiconductor substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59188135A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20150044814A (en) | 2013-10-17 | 2015-04-27 | 가부시끼가이샤 신꼬 몰드 | Method for preparing an electrode pattern of conductive silicone rubber, electrostatic chuck composed entirely of silicone rubber, and method for manufacturing the same |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55122352U (en) * | 1979-02-21 | 1980-08-30 |
-
1983
- 1983-04-08 JP JP6089983A patent/JPS59188135A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55122352U (en) * | 1979-02-21 | 1980-08-30 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20150044814A (en) | 2013-10-17 | 2015-04-27 | 가부시끼가이샤 신꼬 몰드 | Method for preparing an electrode pattern of conductive silicone rubber, electrostatic chuck composed entirely of silicone rubber, and method for manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
JPH0531300B2 (en) | 1993-05-12 |
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