JPH0531300B2 - - Google Patents
Info
- Publication number
- JPH0531300B2 JPH0531300B2 JP58060899A JP6089983A JPH0531300B2 JP H0531300 B2 JPH0531300 B2 JP H0531300B2 JP 58060899 A JP58060899 A JP 58060899A JP 6089983 A JP6089983 A JP 6089983A JP H0531300 B2 JPH0531300 B2 JP H0531300B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- electrodes
- electrode
- surface treatment
- adsorption
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 12
- 238000004381 surface treatment Methods 0.000 claims description 9
- 230000000694 effects Effects 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000001816 cooling Methods 0.000 claims description 4
- 238000009832 plasma treatment Methods 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 238000001179 sorption measurement Methods 0.000 description 19
- 239000010408 film Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000498 cooling water Substances 0.000 description 3
- 239000000428 dust Substances 0.000 description 3
- 229920001971 elastomer Polymers 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67109—Apparatus for thermal treatment mainly by convection
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/50—Substrate holders
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
- H01L21/6833—Details of electrostatic chucks
Description
【発明の詳細な説明】 (イ) 発明の技術分野 本発明は半導体基板の表面処理方法に関する。[Detailed description of the invention] (b) Technical field of the invention The present invention relates to a method for surface treatment of a semiconductor substrate.
(ロ) 従来技術と問題点
半導体装置の製造プロセスでは半導体基板を処
理装置内に固定する必要が生ずる。従来、真空蒸
着法が用いられているが、減圧下で処理する場合
に吸着力が弱くなり不適当である。そこで、そう
した不都合のない静電吸着も利用されるが、次の
様な問題がある。(b) Prior Art and Problems In the manufacturing process of semiconductor devices, it is necessary to fix the semiconductor substrate within the processing equipment. Conventionally, a vacuum evaporation method has been used, but the adsorption force becomes weak when processing under reduced pressure, making it unsuitable. Therefore, electrostatic adsorption, which does not have such disadvantages, is used, but it has the following problems.
第１図は静電吸着法を説明する模式図である第
１図では、平面電極１上に形成された絶縁性薄膜
２の上に、半導体基板３を載置し、電極１と半導
体基板３の間に電圧を印加することによつて基板
３を吸着している。かかる静電吸着法において吸
着力を高めるためには、絶縁膜の厚さを薄くする
か印加電圧を上げる必要がある。しかし、この方
法は相反するところがある。すなわち、絶縁破壊
を防ぐために、絶縁膜をうすくすると印加電圧を
下げなければならず、逆に印加電圧を上げると絶
縁膜を厚く形成しなければならないからである。
更に、絶縁膜は樹脂で作成されるので、熱伝導性
が悪く、そのために半導体基板の冷却が困難であ
る。 FIG. 1 is a schematic diagram for explaining the electrostatic adsorption method. In FIG. 1, a semiconductor substrate 3 is placed on an insulating thin film 2 formed on a flat electrode 1, and the electrode 1 and the semiconductor substrate 3 are By applying a voltage between them, the substrate 3 is attracted. In order to increase the adsorption force in such an electrostatic adsorption method, it is necessary to reduce the thickness of the insulating film or increase the applied voltage. However, this method has some contradictions. That is, in order to prevent dielectric breakdown, making the insulating film thinner requires lowering the applied voltage, and conversely, increasing the applied voltage requires forming the insulating film thicker.
Furthermore, since the insulating film is made of resin, it has poor thermal conductivity, making it difficult to cool the semiconductor substrate.
(ハ) 発明の目的
本発明は、以上の如き従来技術の現状に鑑み、
半導体基板を容易かつ強力に吸着し、しかも冷却
効率の良い吸着方法を提供することを目的とす
る。(c) Purpose of the invention In view of the current state of the prior art as described above, the present invention has been made to
It is an object of the present invention to provide a suction method that easily and strongly suctions a semiconductor substrate and has good cooling efficiency.
(ニ) 発明の構成
本発明は、上記目的を達成するために、半導体
基板の一表面側でこれを支持し、両者の間を電気
的に分離する間〓を有し、且つ互いに略対称とな
るように配置された略同形状を有する、金属より
も大きな抵抗を有する物質からなる第１及び第２
の電極と、
該第１及び第２の電極間に電位差を生じせしめ
る電圧供給手段とを有し、
半導体基板を第１及び第２の電極の両方の表面
上に直接に載置し、第１及び第２の電極と基板と
のそれぞれの間にジヨンセン・ラーベク効果を生
じせしめ、基板を第１及び第２の電極に吸着させ
た状態で表面処理を行うことを特徴とする半導体
基板の表面処理方法を提供する。(d) Structure of the Invention In order to achieve the above object, the present invention supports a semiconductor substrate on one surface side, has a gap electrically separating the two, and is substantially symmetrical to each other. The first and second parts are made of a material having a higher resistance than metal, and have substantially the same shape and are arranged so that the
and voltage supply means for generating a potential difference between the first and second electrodes, the semiconductor substrate is placed directly on the surfaces of both the first and second electrodes, and the semiconductor substrate is placed directly on the surfaces of both the first and second electrodes, and surface treatment of a semiconductor substrate, characterized in that the surface treatment is performed with the substrate adsorbed to the first and second electrodes by creating a Jijonsen-Rahbek effect between each of the second electrode and the substrate. provide a method.
(ホ) 発明の実施例
本発明で利用するジヨンセン・ラーベク
（Johnsen−Rahbek）効果とは、半導体と金属ま
たは半導体と半導体を面で接触させ、200V程度
の電圧を印加するとそれらの間に吸着力が働く現
像をいう。半導体を金属または半導体に面で接触
させると、微視的には両者は僅小な点で接触し、
10-5〜10-7cm程度の小間隙をもつ平行平板コンデ
ンサの両電極と等価な状態になり、吸着力を生ず
るのである。この吸着力Ｆを式で表わすと
Ｆ＝１／２ε（Ｖ／ｄ）2S
ε＝εrε0
式中、ε：小間隙の誘電率
Ｖ：印加電圧
ｄ：小間隙の大きさ
Ｓ：接触面積
εr：１〜10
ε0：8.9×10-12〔C2N-1m-2〕
である。単位面積当りの吸着力を試算するために
εr＝１、ε0＝8.9×10-12〔C2N-1cm-2〕、Ｖ＝200
〔Ｖ〕、ｄ＝10-7〔ｍ〕、Ｓ＝10-4〔m2〕を代入する
と、Ｆ＝1.78×103〔Ｎ〕＝1.74×104Kg重である。
実際にはこの１％程度の吸着力が発生するが、そ
れでも吸着力は大きい（静電吸着の約100倍）。(E) Embodiments of the Invention The Johnsen-Rahbek effect utilized in the present invention is that when a semiconductor and a metal or a semiconductor and a semiconductor are brought into surface contact and a voltage of about 200V is applied, an attractive force is created between them. This refers to development in which When a semiconductor is brought into surface contact with a metal or a semiconductor, microscopically they contact each other at a very small point.
The state is equivalent to that of the electrodes of a parallel plate capacitor with a small gap of about 10 -5 to 10 -7 cm, and an attractive force is generated. This adsorption force F is expressed by the formula: F=1/2ε(V/d) 2 S ε=ε r ε 0In the formula, ε: Dielectric constant of the small gap V: Applied voltage d: Size of the small gap S: Contact area ε r : 1 to 10 ε 0 : 8.9×10 −12 [C 2 N −1 m −2 ]. To estimate the adsorption force per unit area, ε r = 1, ε 0 = 8.9×10 -12 [C 2 N -1 cm -2 ], V = 200
Substituting [V], d=10 -7 [m], and S=10 -4 [m 2 ], F=1.78×10 3 [N]=1.74×10 4 Kg weight.
In reality, an adsorption force of about 1% of this is generated, but the adsorption force is still large (approximately 100 times that of electrostatic adsorption).
本願発明は、高抵抗電極とウエハを直接接触さ
せ、両者に生ずる電位差により吸着する。本願発
明では、電極として大きな電気抵抗を有する物質
を用いて、微視的な電極とウエハが接触しない部
分での両者の電位差を高めて、両者を強力に吸引
することを可能にしている。従つて、電極にウエ
ハを安定して吸着することができる。また、電極
の電気抵抗が大きいため、ウエハに流れる電流を
小さくすることができ、ウエハ上に形成したデバ
イスへのダメージを抑制することができる。 In the present invention, a high-resistance electrode and a wafer are brought into direct contact with each other, and the wafer is attracted to the wafer by the potential difference generated between the two. In the present invention, a material having a large electrical resistance is used as the electrode to increase the potential difference between the microscopic electrode and the wafer at a portion where they do not come into contact with each other, thereby making it possible to strongly attract the two. Therefore, the wafer can be stably attracted to the electrode. Furthermore, since the electrical resistance of the electrode is high, the current flowing through the wafer can be reduced, and damage to devices formed on the wafer can be suppressed.
これに対し、ウエハをクロム等の導電性金属か
らなる電極と直接接触させると、両者の微視的な
接触点から離れた小間〓を有する領域で接触点と
の間の電位差が、高抵抗の電極を用いた場合のよ
うに大きくならないために、吸引力が小さく、本
願発明の効果が得られない。 On the other hand, when a wafer is brought into direct contact with an electrode made of a conductive metal such as chromium, a potential difference between the contact point and the contact point is created by a high resistance Since the suction force is not as large as in the case of using electrodes, the suction force is small and the effect of the present invention cannot be obtained.
しかも、半導体基板を半導体などに直接接触さ
せて置くので半導体基板の冷却効率もよくなる。 Furthermore, since the semiconductor substrate is placed in direct contact with a semiconductor or the like, the cooling efficiency of the semiconductor substrate is improved.
半導体基板と平面電極の間に電圧を印加する方
法は、第２図に示す如く、相互に隔置された対の
平面電極７，８上に半導体基板３を載置し、その
対の平面電極７，８の間に電圧を印加する。 As shown in FIG. 2, the method of applying a voltage between a semiconductor substrate and a plane electrode is to place a semiconductor substrate 3 on a pair of plane electrodes 7 and 8 spaced apart from each other, and A voltage is applied between 7 and 8.
第３図は本発明の具体的な１実施例であるブラ
ズマエツチング装置を概略的に示す。気密にした
処理室１０はガス導入口１１およびガス排出口１
２を有し、ガス排出口１２にはバルブ１３を介し
て排気ポンプ１４が接続され、処理室１０内は減
圧にされる。シリコンウエーハ等の被処理基板１
５は、処理室１０の吸着板（平面電極）１６，１
７の上に載置されている。吸着板（平面電極）１
６，１７は、同一平面をなす平坦な上面を有しか
つ相互間は厳格に隔置された対をなす例えばＰ形
シリコン半導体の個片である。相互に絶縁された
吸着板１６，１７に電源１８から200〜400V程度
の電圧を印加すると、各吸着板１６，１７と半導
体基板１５の間にも電圧がかかり、ジヨンセン・
ラーベク効果で、半導体基板１５が吸着板１６，
１７に吸着される。 FIG. 3 schematically shows a plasma etching apparatus which is a specific embodiment of the present invention. The airtight processing chamber 10 has a gas inlet 11 and a gas outlet 1.
2, an exhaust pump 14 is connected to the gas exhaust port 12 via a valve 13, and the inside of the processing chamber 10 is reduced in pressure. Processed substrate 1 such as silicon wafer
5 is a suction plate (plane electrode) 16,1 of the processing chamber 10;
It is placed on top of 7. Adsorption plate (plane electrode) 1
Reference numerals 6 and 17 are individual pieces of, for example, P-type silicon semiconductor, which form a pair having flat upper surfaces that are on the same plane and are strictly spaced apart from each other. When a voltage of about 200 to 400 V is applied from the power supply 18 to the mutually insulated suction plates 16 and 17, a voltage is also applied between each suction plate 16 and 17 and the semiconductor substrate 15, causing
Due to the Rahbek effect, the semiconductor substrate 15 is attached to the suction plate 16,
17 is adsorbed.
吸着板（平面電極）１６，１７はAl2O3等の絶
縁板１９を介して支持され、その支持体２０には
水冷の設備が施されている。冷却水は冷却水入口
２２から入り、支持体２０の空洞２１の中を循環
し、冷却水出口２３から外へ出る。吸着板１６，
１７の上方には電極２４があり、高周波電源２５
から供給される電週波電力の一方の電極をなして
いる。この高周波電力がガス導入口から処理室内
に導入されたガスをプラズマ化し、そのプラズマ
ガスが半導体基板１５をエツチングする。プラズ
マエツチング装置のその他の構成は慣用のものと
同様である。 The suction plates (plane electrodes) 16 and 17 are supported via an insulating plate 19 made of Al 2 O 3 or the like, and the support 20 is equipped with water cooling equipment. Cooling water enters through the cooling water inlet 22, circulates within the cavity 21 of the support 20, and exits through the cooling water outlet 23. Suction plate 16,
There is an electrode 24 above 17, and a high frequency power source 25
It serves as one electrode for the radio wave power supplied from the This high frequency power converts the gas introduced into the processing chamber from the gas inlet into plasma, and the plasma gas etches the semiconductor substrate 15. The rest of the configuration of the plasma etching apparatus is the same as a conventional one.
吸着板１６，１７は以上の実施例ではＰ型シリ
コン半導体で作成したが、導電性ゴム、例えば、
金属粉末入りの硬質シリコーンゴム（抵抗値Ｒ≦
30Ω・cm-3程度）で作成すれば、ゴム弾性がある
ので、ゴミが吸着板表面に付着しても半導体基板
と吸着板の密着性が阻げられることはない。従つ
て、安定した吸着力が得られ、吸着ミスが防止さ
れる。更に、第４図に示す如く、導電性ゴムの吸
着表面に直径１mm程度の多数の凸部をつくれば、
ゴミ付着のための吸着ミスがより確実に防止され
る。尚、第４図では、簡単のために吸着板即ち両
電極３０，３１を半円形で示したが、実際的には
二重螺旋形など効率の良い電極構造が用いられ、
又それが好ましい。 Although the adsorption plates 16 and 17 were made of P-type silicon semiconductor in the above embodiment, they could also be made of conductive rubber, for example,
Hard silicone rubber containing metal powder (resistance value R≦
If it is made with a resistance of about 30 Ω cm -3 ), it has rubber elasticity, so even if dust adheres to the surface of the suction plate, the adhesion between the semiconductor substrate and the suction plate will not be hindered. Therefore, stable suction force can be obtained and suction errors can be prevented. Furthermore, as shown in Fig. 4, if a large number of protrusions with a diameter of about 1 mm are made on the adsorption surface of the conductive rubber,
Suction errors due to adhesion of dust can be more reliably prevented. In FIG. 4, the suction plates, that is, both electrodes 30 and 31 are shown as semicircles for simplicity, but in reality, an efficient electrode structure such as a double helix shape is used.
Also, that is preferable.
(6) 発明の効果
以上の説明から明らかなように、本発明によ
り、半導体基板と電極の間に電圧を印加するだけ
でその間に絶縁膜を設けることなく半導体基板の
強力な吸着を実現することができる。従つて、絶
縁破壊の心配がなく、しかも、強力な熱伝導性の
良好な吸着が可能になる。本発明による装置は構
成が単純であり、製造容易である。また、ゴミ付
着による吸着ミスを防止することも可能である。(6) Effects of the Invention As is clear from the above description, the present invention makes it possible to achieve strong adsorption of a semiconductor substrate simply by applying a voltage between the semiconductor substrate and the electrode without providing an insulating film therebetween. I can do it. Therefore, there is no fear of dielectric breakdown, and moreover, good adsorption with strong thermal conductivity is possible. The device according to the invention is simple in construction and easy to manufacture. It is also possible to prevent suction errors due to adhesion of dust.
第１図は静電吸着法を説明する断面図、第２図
はジヨンセン・ラーベク効果を利用した吸着法を
説明する断面図、第３図は本発明の１実施例のプ
ラズマエツチング装置の概略断面図、第４図は吸
着板の１態様を示す斜視図である。
１，４，５，６，７，８……平面電極、２……
絶縁膜、３……半導体基板、１０……処理室、１
６，１７……吸着板（平面電極）、１８……電源、
１９……絶縁体、２４……電極、２５……高周波
電源、３０，３１……吸着板。
FIG. 1 is a cross-sectional view explaining the electrostatic adsorption method, FIG. 2 is a cross-sectional view explaining the adsorption method using the Jijonsen-Rahbek effect, and FIG. 3 is a schematic cross-section of a plasma etching apparatus according to an embodiment of the present invention. FIG. 4 is a perspective view showing one embodiment of the suction plate. 1, 4, 5, 6, 7, 8...plane electrode, 2...
Insulating film, 3... Semiconductor substrate, 10... Processing chamber, 1
6, 17... Adsorption plate (plane electrode), 18... Power supply,
19... Insulator, 24... Electrode, 25... High frequency power supply, 30, 31... Adsorption plate.
Claims (1)
の間を電気的に分離する間〓を有し、且つ互いに
略対称となるように配置された略同形状を有す
る、金属よりも大きな抵抗を有する物質からなる
第１及び第２の電極と、 該第１及び第２の電極間に電位差を生じせしめ
る電圧供給手段とを有し、 該半導体基板を該第１及び第２の電極の両方の
表面上に直接に載置し、該第１及び第２の電極と
該基板とのそれぞれの間にジヨンセン・ラーベク
効果を生じせしめ、該基板を該第１及び第２の電
極に吸着させた状態で表面処理を行うことを特徴
とする半導体基板の表面処理方法。 ２ 前記第１及び第２の電極を介してウエハを冷
却しながら前記表面処理を行うことを特徴とする
特許請求の範囲第１項記載の半導体基板の表面処
理方法。 ３ 前記表面処理はプラズマ処理を伴うことを特
徴とする特許請求の範囲第１項または第２項記載
の半導体基板の表面処理方法。[Scope of Claims] 1. Supporting the semiconductor substrate on one surface side, having a space that electrically isolates the semiconductor substrate, and having substantially the same shape arranged so as to be substantially symmetrical to each other. , first and second electrodes made of a substance having a higher resistance than metal, and voltage supply means for generating a potential difference between the first and second electrodes, and the semiconductor substrate is connected to the first and second electrodes. placed directly on both surfaces of a second electrode to create a Jijonsen-Rahbek effect between the first and second electrodes and the substrate, respectively; A method for surface treatment of a semiconductor substrate, characterized in that the surface treatment is performed while the substrate is adsorbed to an electrode. 2. The method for surface treatment of a semiconductor substrate according to claim 1, wherein the surface treatment is performed while cooling the wafer via the first and second electrodes. 3. The method for surface treatment of a semiconductor substrate according to claim 1 or 2, wherein the surface treatment involves plasma treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6089983A JPS59188135A (en) | 1983-04-08 | 1983-04-08 | Attracting method of semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6089983A JPS59188135A (en) | 1983-04-08 | 1983-04-08 | Attracting method of semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59188135A JPS59188135A (en) | 1984-10-25 |
| JPH0531300B2 true JPH0531300B2 (en) | 1993-05-12 |
Family
ID=13155661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6089983A Granted JPS59188135A (en) | 1983-04-08 | 1983-04-08 | Attracting method of semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59188135A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6217303B2 (en) | 2013-10-17 | 2017-10-25 | 株式会社シンコーモールド | Method for producing electrode pattern made of conductive silicone rubber, all-silicone rubber electrostatic chuck and method for producing the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55122352U (en) * | 1979-02-21 | 1980-08-30 |
-
1983
- 1983-04-08 JP JP6089983A patent/JPS59188135A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59188135A (en) | 1984-10-25 |
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