JPS5918795B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and particularly to a floating gate type nonvolatile memory.

A semiconductor memory device using a semiconductor memory transistor (hereinafter referred to as a memory transistor) having a floating gate as a nonvolatile memory uses the source potential of the memory transistor as a reference potential, and there is a voltage between this reference potential and the semiconductor substrate forming the transistor. Write and read operations are performed by applying a required bias voltage called back gate voltage.

This bias voltage is preferable in order to control the gate threshold voltage of transistors for peripheral circuits formed within the same semiconductor substrate and to speed up circuit operation. However, the bias effect of the back gate voltage on the memory transistor accelerates carriers in the depletion metal spreading from the source junction, which accompanies carrier injection during read operations, which degrades memory retention characteristics. .
An object of the present invention is to provide a semiconductor memory device with good memory retention characteristics.

In the semiconductor memory device of the present invention, in an integrated circuit in which a semiconductor memory transistor having a floating gate and a circuit control transistor are provided on a common semiconductor base, the source potential of the memory transistor is set between the source potential of the memory transistor and the base during a write operation. A semiconductor memory device according to the present invention is characterized in that a control circuit is provided to set the reference potential having a required potential difference to the base potential during a read operation. The memory retention characteristics are improved because carrier injection can be prevented by guaranteeing the circuit operation and setting the source potential of the storage transistor to the base potential during the read operation.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

This embodiment has a decode circuit 11, a memory circuit 12, and a control circuit 13 in an integrated circuit. The decode circuit 11 and the control circuit 13 constitute electronic circuits using ordinary silicon gate transistors, and the memory circuit 12 is connected to the row line D. ,
D1... and column line W. , W1... are connected to the switching transistors Qll, Q12 at the matrix intersections formed by
, Q21, Q22 and storage transistors M,0, M12,
It has a memory cell circuit in which one M24 and one M22 are combined. Memory transistor Mll, M123M213
M22 is a nonvolatile memory transistor having a floating gate, whose control gate electrodes are commonly connected to the gate line SG, and whose sources are commonly connected to the potential control line BB. Switching transistors Qll3Q12, Q21, Q22
is a normal silicon gate type transistor, and its source is connected to the drains of storage transistors M113M12 and M213M22, respectively, and the drain is connected to the row line of each row, and the gate is connected to the column line of each column.〇The potential control line BB is Transistors Qw and Q provided in the control circuit 13
Connects to the drain of R. The transistor Qw whose gate is driven by the write signal W has its source connected to the reference potential GND, and the transistor QR whose gate is driven by the read signal R.
The source of is connected to the base potential line SB. This embodiment operates with a substrate potential of -3 to -10, and when writing, the ? conducts to write predetermined information into each memory cell using the potential of the potential control line BB, that is, the potential of the source of the memory transistor as a reference potential. This information is the amount of charge accumulated in the floating gate of the storage transistor. This results in a difference in gate thresholds.

However, if the potential of the potential control line is at the reference potential during the read operation, leakage electrons will accelerate in the source junction depletion layer of the storage transistor, causing fluctuations in the amount of floating charge. The potential of the potential control line BB is made conductive, that is, the source of the memory transistor is set to the base potential SB. FIG. 2 is a characteristic diagram showing the change in accumulated charge Q over time in the embodiment shown in FIG.

The time change from the initial stage when the accumulated charge is a positive charge is
When the basic potential is -5V and the gate line SG is 0V, and the potential of the potential control line is 0V, the half-life is 105 hours as shown in characteristic curve a. On the other hand, if the potential control line is forced to the substrate potential during reading by the control circuit as in this embodiment, a half-life of 1010 or more can be achieved as shown in characteristic curve b, and the non-volatility characteristics are significantly improved. be able to. However, the same effect can be obtained even if the transistor Qw controlled by the write signal in the embodiment of FIG. 1 is removed.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, and Fig. 2 is a characteristic diagram showing the effects of an embodiment of the invention. be.

Claims (1)

[Claims] 1. In an integrated circuit in which a nonvolatile storage transistor and a circuit control transistor are provided on a common semiconductor substrate, the source potential of the storage transistor is set as a reference potential having a required potential difference with the substrate during a write operation, and the readout 1. A semiconductor memory device comprising a control circuit that approaches the base potential during operation.