CA1079865A - Semiconductor integrated circuit device composed of insulated gate field-effect transistors - Google Patents
Semiconductor integrated circuit device composed of insulated gate field-effect transistorsInfo
- Publication number
- CA1079865A CA1079865A CA327,604A CA327604A CA1079865A CA 1079865 A CA1079865 A CA 1079865A CA 327604 A CA327604 A CA 327604A CA 1079865 A CA1079865 A CA 1079865A
- Authority
- CA
- Canada
- Prior art keywords
- transistors
- integrated circuit
- circuit device
- semiconductor integrated
- matrix
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Abstract
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
COMPOSED OF INSULATED GATE FIELD-EFFECT TRANSISTORS
Abstract of the Disclosure In a semiconductor integrated circuit device composed of insulated gate field-effect transistors, the improvement comprising the facts that the insulated gate field-effect transistors having gate insulating films of substantially equal thicknesses are arranged on a principal surface of a semiconductor substrate in the shape of a matrix, that gate input columns of the transistors are formed of polycrystal silicon layers, and that some of the transistors are made the enhancement type, while the others are made the depletion type. Further, the respective transistors are formed by the self-alignment technique which employs the polycrystal silicon layers as a diffusion mask, and the depletion type transistors are formed by implanting impurity ions opposite in the conductivity type to the substrate into selected areas of the surface of the substrate. Thus, a read only memory in a MOS-IC chip has its occupying area reduced remarkably.
COMPOSED OF INSULATED GATE FIELD-EFFECT TRANSISTORS
Abstract of the Disclosure In a semiconductor integrated circuit device composed of insulated gate field-effect transistors, the improvement comprising the facts that the insulated gate field-effect transistors having gate insulating films of substantially equal thicknesses are arranged on a principal surface of a semiconductor substrate in the shape of a matrix, that gate input columns of the transistors are formed of polycrystal silicon layers, and that some of the transistors are made the enhancement type, while the others are made the depletion type. Further, the respective transistors are formed by the self-alignment technique which employs the polycrystal silicon layers as a diffusion mask, and the depletion type transistors are formed by implanting impurity ions opposite in the conductivity type to the substrate into selected areas of the surface of the substrate. Thus, a read only memory in a MOS-IC chip has its occupying area reduced remarkably.
Description
Background of the Invention (1) Field of the Invention This invention relates to an integrated circuit de~ice composed of insulated gate field-effect transistors (hereinbelow termed "MOSIC") and also to a method of manu-facturing the same.
(2) Description of the Prior Art In general, the MOSIC uses aluminum or silicon as the material of a gate electrode. On the other hand, there 10 are known integrated circuits (IC) in which, in an inverter -stage forming one internal circuit thereof, a load MOSFET of the enhancement mode is employed as the load of a driving MOSFET operative in the enhancement mode (hereinafter called "E/E type IC") and the IC in which a~load MOSFET of the depletion mode is employed (hereinafter called "E/D type IC").
Among the IC's, the silicon gate MOSIC employing the depletion load has recently come into extensive use as a device which is I of higher performance for various uses and has a higher ; density of integration ~han the aluminum gate MOSIC. According to experiments by the inventor, the occupying area of an Si gate MOS transistor having a self-aligned gate structure is reduced by approximately 2~ to 30% as compared with that of an . Al gate MOS transistor.
As the result of the investigation of MOSIC's commercially available as produced by se~eral manufacturers, however, it has been found that, in a read only memory (here- ~
inbelow abbreviated to "ROM") which occupies a considerable : :
part of a MOSIC chip, the size of the single bit of the ROM : :
is not always significant~y smaller in the conventional Si gate ROM structure than in the Al gate one as indicated in the follo~ing Table 1:
- , . - : ~, . : . . .
.: .~ . :, .
: . : .
. .
1~798bi5 ;
Table 1: Comparisons of ROM bit sizes : IC manufacturer Si gate ROM Al gate ROM type of IC
A _ ~m 336 ~m2 dynamic type B 616 650 static type D 412 _ ll . _ 441 432 ., Summary of the Invention It is accordingly the principal object of this invention to provide a novel ROM structure which is conspi-cuously smaller in occupying area than the prior-art Al gate or Si gate ROM's, and a method of manufacturing such novel ROM structure.
Another object of this invention is to provide an IC in which the occupying area of a ROM per unit function in the prior-art MOSIC of the Si gate E/D type is conspicuously diminished, and a method of manufacturing such IC.
According to one aspect of this invention, there is provided a semiconductor integrated circuit device comprising: a semiconductor body having one conductivity type; a plurality of first insulated gate field-effect ~, transistors each having a source, a drain and a gate and being arranged in and on said body in a matrix form in which said transistors are disposed along a plurality of rows and columns and the transistors in each row are . connected in series; a plurality of second insulated gate field-effect transistors each source electrode of which is connected in series with the drain of the first transis~or connected at one end of each row and to each gate of which ., :
~ - 2 -;
~ . ~. . .
, 10~865 a first clock pulse is applied and wherein the clock controlled second transistors are enhancement type and selected ones of the transistors in said matrix are depletion type and the gates of the transistors in each column of said matrix are formed of a common gate electrode layer.
Other aspects of this invention are claimed in our Canadian patent application Serial No. 240,274 filed on November 24, 1975, of which the present application is a division, and in other applications divided therefrom.
According to another feature of the invention, at least in preferred forms, the respective tran-sistors are formed by a self-alignment technique which employs the polycrystal silicon layer as a - 2a -.
.
- . .
. . : .
, :. , . '. :
:
-diffusion mask. The depletion type transistors are formedby implantin~ impurity ions opposite in conductivity type to the substrate into selected areas of the surface of the substrate.
Brief Description of the Drawings FIG. 1 is a fundamental circuit diagram of a prior-art MOSROM, FIGs. 2(a) and 2(b) are enlarged plan and sectional views of a part of the prior-art MOSROM, respecti~ely, FIG. 3 is a fundamental circuit diagram of a MOSROM
according to this invention, FIGs. 4(a) and 4(b) as well as 4(c) are enlarged plan and sectional views of a part of the MOSROM according to this invention, respectively, FIG. S is a diagram of a circuit which uses the MOSROM according to this invention, FIGs. 6(a) to 6(f) and FIGs. 7(a) to 7(d) are enlarged sectional views and plan views of a part of the MOSROM .
according to this invention for explaining a manufacturing :
20 process of the MOSROM, respectively, . :
FIGs. 8(a) and 8(b) are top pattern diagrams of LSI chips of a MOSLSI utilizing this invention and a MOSLSI
fabricated by a prior art technique for making a comparison therebetween, respectively, and FIG. 9(b) is a diagram showing an example of a circuit in the case of actually employing the MOSROM of this .
invention, while FIG. 9(a) is a graph showing the measured results of operating speeds in the circuit of FIG. 9(b).
Descriptiorl of the Preferred Embodiments Hereunder the improved ROM (MOS matrix) according to this invention will be described in detail in comparison ~.
, . . .
~0798~S
with a prior-art Si gate ROM with reference to the drawings.
FIG. 1 shows the fundamental circuit which is used in the prior-art Si gate ROM. FIG. 2(a) is a plan view showing a part of the prior-art Si gate ROM on an enlarged scale, while FIG. 2(b) is a sectional view of the part of the prior-art Si gate MOSROM as taken along a line X - X' in FIG.
2(a).
As illustrated in FIG. 1, the prior-art Si gate MOSROM consists of MOSFET's which are arranged in parallel.
The states of the respective memory cells are discriminated by the thicknesses of gate oxide films. A signal of low level close to a supply voltage is applied to a selected address line, whereas a signal of high level close to 0 (zero) volt is applied to an unselected address l~ne. Considering by way of example a case where a line IN2 is selected, the MOSFET
underlying this line has a thick gate oxide film and is usually "off," so that the output level becomes the low level. As shown in FIGs. 2(a) and 2(b), such prior-art ROM
is constructed of P -type diffused layers 2, 3 and 4; poly-crystal silicon layers 7 and 8; silicon dioxide films 5 and 6; phosphosilicate glass 9; a through-hole 11; and an aluminum layer 10. The polycrystal silicon layer is used as ah address input line, while the aluminum layer is used as an output line. The through-holes between the Al layer and the P -type diffused layers are necessary for commonly connecting the drain electrodes of the MOSFET's wnich are arranged at each row. As apparent from the figures, the states of the memory cells at the points of intersection between the input lines and the output lines are determined by the thicknesses of the gate oxide films. More specifically, where the MOSFET which conducts the "on-off" operation by the signal voltages . . . ~ . :
.
.
applied to the input line is necessary at a certain point of intersection, the gate oxide film beneath the polycrystal Si layer at that place is made thin, while at the place where the MOSFET which conducts such operation is unnecessary, the oxide operation is unnecessary, the oxide film beneath the poly- -crystal Si layer at that place is made thick. ThuS, the ~OM
having a predetermined bit pattern is constructed. The minimum size per ~nit bit of the Si gate ROM of such construction is about 410 ~m2,and it is substantially equal to that of the Al gate ROM.
As described a~ove, the conventional ROM is character-ized by the following con~truction:
(1) The states of the respective memory cells are dis-tingùishèd by the thickness of the gate oxide films.
(2) Since the self-aligned gate structure is adopted, the polycrystal layer cannot cross over the P -type diffused layer. Therefore,the Al wiring layer is necessitated, and the through-hole is required between the P+-type diffused layer and the Al layer.
Accordingly, the occupying area per bit of the prior-art Si gate ROM cannot be made small in spite of the adoption of the self-aligned structure.
The Si gate MOSROM according to this invention will now be explained with reference to Fig. 3, Figs 4(a), 4(b) and 4(c), and Fig. 5.
Fig. 3 shows the fundamental circuit which is employed in the ROM according to this invention. It is composed o a plurality of enhancement mode and depletion mode MOSFET's ; which are connected in series as driving elements. The deple-tion mode MOSFET functions also as one resistance element. A
read-out is stably executed in such way that a signal of high 1~798fi5 level close to 0 (zero) volt is impressed on a selected address line. At thi5 time, a signal of low level is impressed on an unselected address line.
By way of example, in case where the address line IN2 is selected, the MOSFET underlying this address line IN2 turns "on" as it is the depletion mode MOSFET. Since the MOSFET's associated with the other address lines INl, IN3, ..... and INn are the enhencement mode MOSFET's they turn "on" by having the low level signal applied to their gates. Since the MOSFET
associated with the address line INn 1 is the depletion modP
MOSFET, it is "on" even when the low level signal is applied to its gate. In this case, accordingly, all the driving elements are substantially "on," so that an output signal of high level close to 0 (zero) volt is produced at an output terminal OUT.
On the other hand, in case where the address line IN3 is selected,~the MOSFET associated with this line becomes the nonconductive (off) state by the input signal of high level as it operates in the enhancement mode. Therefore, an output signal of low level appears at the output terminal OUT.
As apparent from the above explanation, in the ROM
according to this invention, the output data line to be pre-charged holds the low level or is shifted to the high level in dependence on whether the enhancement or depletion made MOSFET
is addressed, respectively.
Fig. 5 shows a ROM circuit which is constructed by applying this invention to an actual ROM of MOSIC on the basis of the fundamental circuit of the invention illustrated in Fig.
Among the IC's, the silicon gate MOSIC employing the depletion load has recently come into extensive use as a device which is I of higher performance for various uses and has a higher ; density of integration ~han the aluminum gate MOSIC. According to experiments by the inventor, the occupying area of an Si gate MOS transistor having a self-aligned gate structure is reduced by approximately 2~ to 30% as compared with that of an . Al gate MOS transistor.
As the result of the investigation of MOSIC's commercially available as produced by se~eral manufacturers, however, it has been found that, in a read only memory (here- ~
inbelow abbreviated to "ROM") which occupies a considerable : :
part of a MOSIC chip, the size of the single bit of the ROM : :
is not always significant~y smaller in the conventional Si gate ROM structure than in the Al gate one as indicated in the follo~ing Table 1:
- , . - : ~, . : . . .
.: .~ . :, .
: . : .
. .
1~798bi5 ;
Table 1: Comparisons of ROM bit sizes : IC manufacturer Si gate ROM Al gate ROM type of IC
A _ ~m 336 ~m2 dynamic type B 616 650 static type D 412 _ ll . _ 441 432 ., Summary of the Invention It is accordingly the principal object of this invention to provide a novel ROM structure which is conspi-cuously smaller in occupying area than the prior-art Al gate or Si gate ROM's, and a method of manufacturing such novel ROM structure.
Another object of this invention is to provide an IC in which the occupying area of a ROM per unit function in the prior-art MOSIC of the Si gate E/D type is conspicuously diminished, and a method of manufacturing such IC.
According to one aspect of this invention, there is provided a semiconductor integrated circuit device comprising: a semiconductor body having one conductivity type; a plurality of first insulated gate field-effect ~, transistors each having a source, a drain and a gate and being arranged in and on said body in a matrix form in which said transistors are disposed along a plurality of rows and columns and the transistors in each row are . connected in series; a plurality of second insulated gate field-effect transistors each source electrode of which is connected in series with the drain of the first transis~or connected at one end of each row and to each gate of which ., :
~ - 2 -;
~ . ~. . .
, 10~865 a first clock pulse is applied and wherein the clock controlled second transistors are enhancement type and selected ones of the transistors in said matrix are depletion type and the gates of the transistors in each column of said matrix are formed of a common gate electrode layer.
Other aspects of this invention are claimed in our Canadian patent application Serial No. 240,274 filed on November 24, 1975, of which the present application is a division, and in other applications divided therefrom.
According to another feature of the invention, at least in preferred forms, the respective tran-sistors are formed by a self-alignment technique which employs the polycrystal silicon layer as a - 2a -.
.
- . .
. . : .
, :. , . '. :
:
-diffusion mask. The depletion type transistors are formedby implantin~ impurity ions opposite in conductivity type to the substrate into selected areas of the surface of the substrate.
Brief Description of the Drawings FIG. 1 is a fundamental circuit diagram of a prior-art MOSROM, FIGs. 2(a) and 2(b) are enlarged plan and sectional views of a part of the prior-art MOSROM, respecti~ely, FIG. 3 is a fundamental circuit diagram of a MOSROM
according to this invention, FIGs. 4(a) and 4(b) as well as 4(c) are enlarged plan and sectional views of a part of the MOSROM according to this invention, respectively, FIG. S is a diagram of a circuit which uses the MOSROM according to this invention, FIGs. 6(a) to 6(f) and FIGs. 7(a) to 7(d) are enlarged sectional views and plan views of a part of the MOSROM .
according to this invention for explaining a manufacturing :
20 process of the MOSROM, respectively, . :
FIGs. 8(a) and 8(b) are top pattern diagrams of LSI chips of a MOSLSI utilizing this invention and a MOSLSI
fabricated by a prior art technique for making a comparison therebetween, respectively, and FIG. 9(b) is a diagram showing an example of a circuit in the case of actually employing the MOSROM of this .
invention, while FIG. 9(a) is a graph showing the measured results of operating speeds in the circuit of FIG. 9(b).
Descriptiorl of the Preferred Embodiments Hereunder the improved ROM (MOS matrix) according to this invention will be described in detail in comparison ~.
, . . .
~0798~S
with a prior-art Si gate ROM with reference to the drawings.
FIG. 1 shows the fundamental circuit which is used in the prior-art Si gate ROM. FIG. 2(a) is a plan view showing a part of the prior-art Si gate ROM on an enlarged scale, while FIG. 2(b) is a sectional view of the part of the prior-art Si gate MOSROM as taken along a line X - X' in FIG.
2(a).
As illustrated in FIG. 1, the prior-art Si gate MOSROM consists of MOSFET's which are arranged in parallel.
The states of the respective memory cells are discriminated by the thicknesses of gate oxide films. A signal of low level close to a supply voltage is applied to a selected address line, whereas a signal of high level close to 0 (zero) volt is applied to an unselected address l~ne. Considering by way of example a case where a line IN2 is selected, the MOSFET
underlying this line has a thick gate oxide film and is usually "off," so that the output level becomes the low level. As shown in FIGs. 2(a) and 2(b), such prior-art ROM
is constructed of P -type diffused layers 2, 3 and 4; poly-crystal silicon layers 7 and 8; silicon dioxide films 5 and 6; phosphosilicate glass 9; a through-hole 11; and an aluminum layer 10. The polycrystal silicon layer is used as ah address input line, while the aluminum layer is used as an output line. The through-holes between the Al layer and the P -type diffused layers are necessary for commonly connecting the drain electrodes of the MOSFET's wnich are arranged at each row. As apparent from the figures, the states of the memory cells at the points of intersection between the input lines and the output lines are determined by the thicknesses of the gate oxide films. More specifically, where the MOSFET which conducts the "on-off" operation by the signal voltages . . . ~ . :
.
.
applied to the input line is necessary at a certain point of intersection, the gate oxide film beneath the polycrystal Si layer at that place is made thin, while at the place where the MOSFET which conducts such operation is unnecessary, the oxide operation is unnecessary, the oxide film beneath the poly- -crystal Si layer at that place is made thick. ThuS, the ~OM
having a predetermined bit pattern is constructed. The minimum size per ~nit bit of the Si gate ROM of such construction is about 410 ~m2,and it is substantially equal to that of the Al gate ROM.
As described a~ove, the conventional ROM is character-ized by the following con~truction:
(1) The states of the respective memory cells are dis-tingùishèd by the thickness of the gate oxide films.
(2) Since the self-aligned gate structure is adopted, the polycrystal layer cannot cross over the P -type diffused layer. Therefore,the Al wiring layer is necessitated, and the through-hole is required between the P+-type diffused layer and the Al layer.
Accordingly, the occupying area per bit of the prior-art Si gate ROM cannot be made small in spite of the adoption of the self-aligned structure.
The Si gate MOSROM according to this invention will now be explained with reference to Fig. 3, Figs 4(a), 4(b) and 4(c), and Fig. 5.
Fig. 3 shows the fundamental circuit which is employed in the ROM according to this invention. It is composed o a plurality of enhancement mode and depletion mode MOSFET's ; which are connected in series as driving elements. The deple-tion mode MOSFET functions also as one resistance element. A
read-out is stably executed in such way that a signal of high 1~798fi5 level close to 0 (zero) volt is impressed on a selected address line. At thi5 time, a signal of low level is impressed on an unselected address line.
By way of example, in case where the address line IN2 is selected, the MOSFET underlying this address line IN2 turns "on" as it is the depletion mode MOSFET. Since the MOSFET's associated with the other address lines INl, IN3, ..... and INn are the enhencement mode MOSFET's they turn "on" by having the low level signal applied to their gates. Since the MOSFET
associated with the address line INn 1 is the depletion modP
MOSFET, it is "on" even when the low level signal is applied to its gate. In this case, accordingly, all the driving elements are substantially "on," so that an output signal of high level close to 0 (zero) volt is produced at an output terminal OUT.
On the other hand, in case where the address line IN3 is selected,~the MOSFET associated with this line becomes the nonconductive (off) state by the input signal of high level as it operates in the enhancement mode. Therefore, an output signal of low level appears at the output terminal OUT.
As apparent from the above explanation, in the ROM
according to this invention, the output data line to be pre-charged holds the low level or is shifted to the high level in dependence on whether the enhancement or depletion made MOSFET
is addressed, respectively.
Fig. 5 shows a ROM circuit which is constructed by applying this invention to an actual ROM of MOSIC on the basis of the fundamental circuit of the invention illustrated in Fig.
3, and which comprises the first address decoder MOS matrix and the second MOS matrix receiving an output of the first MOS
matrix as its input. A flip-flop circuit 21 consists of a plurality of stages (for example, k/2 stages) connected in - , .. .
iO79865 , cascade. Outputs from the respective stages are delivered directly or through inverter circuits 22 into the first MOS
matrix 23, whose outputs are delivered into the second MOS
matrix 24. The second MOS matrix provides outputs ~UT l to OUT n~ The matrices 23 and 24 have one MOSFET operative in the depletion or enhancement mode in any of the places in which input lines and output lines intersect. Such FET's are connected in series between a supply voltage VDD and a reference potehtial source (earth) at every column. Connected to the respective matrices as loads of the driving MOSFET's are enhancement mode MOSFET's (27, 28) which have clock signals applied to the gates thereof. In the figure, the driving MOSFET's with circles as indicated at 25 are those operating in the depletion mode, while the other driving MOSFET's are those operating in the enhancement mode. Each of the plurality of inverters 22 consists of a driving MOSFET
~' which operates in the enhancement mode, and a load MOSFET
which is connected in series therewith and which operates in the depletion mod~. As will be stated later, all the MOSFET's in the figure have gate insulating films (for ' example, Si02 films) of substantially equal thicknesses (about 500 to 1,500 angstroms) irrespective of the depletion mode or the enhancement mode. The depletion MOSFET's in the MOS
matrices are formed simultaneously with the depletion MOSFET's in the inverters 22 by quite an identical process.
The input lines of the first ahd second matrices are formed of polycrystal silicon wiri~ng layers, while the connection , from the output line of the first matrix to the input line of the secon~ matrix is performed by the use of an aluminum wiring wHich connects a P+-type diffused layer and the poly-crystal Si layer. When FIG. 5 is studied with reference to _ 7 : ~ . ' .
.. . . ...
1~798t;5 FIG. 3, the operation o~ the circuit in FIG. 5 Will be self-explanatory. To be particularly mentioned is that clock pulses ~1 and ~2 whose phases differ from each other are impressed on the gates of the load MOSFET's in the first and second matrices, respectively, and that the amplitudes of these pulses (for example, -12 to -16 volts) are greater than the amplitude of the supply volatge VDD (for example, -6 volts).
Referring now to FIGs. 4(a), 4(b) and 4(c), the ; device structure of the MOSROM according to this invention will be described. FIG. 4(a) is a plan view with a part of the MOSROM enlarged,while FIGs. 4(b) and 4(c) show X - X' and Y - Y' sections in FIG. 4(a), respectively. In the figures, numeral 31 designates an N-type single crystal Si substrate; numerals 32 to 34 and numerals 47 to 49 P+-type diffused layers which are formed by being self-aligned by Si gate electrodes; numerals 35, 36 and 43 gate insulating films of silicon dioxide which have essentially equal thick~
nesses (about 1,000 A); numerals 37 and 38 input lines of polycrystal Si, numeral 39 an insulating film of phosphosili-cate glass; numerals 41 and 42 P-type channel layers which are formed by implanting P-type impurity ions into selected areas of the surface of the substrate in order to form the depletion ~OSFET's;and numerals 44 to 46 field insulating films of silicon dioxide which are comparatively thick (about 1 to 2 ~). As apparent from the figures, one memory cell is formed in any of the places of in~ersection between the polycrystal Si wiring layers (37, 38) as the address input lines and the P -type diffused layers as the self-connected data output lines. The states of the respective memory cells are determined by the presence or absence of . .
107~865 .. .
the P-type channel formed by the ion implantation. All the memory cells have the thin gate oxide films so as to o~erate as the enhancement or depletion MOSFET.
As seen from the figures, the MOS matrix according to this invention has the self-aligned gate structure and needs n~ through-hole. It is there~ore understood that the ~ occupying area to the single bit is remarkably smaller in - the MOS matrix of this invention than in the prior-art one.
FIGs. 8(a) and 8(b) show by comparison the semiconductor chip sizes and the occupying areas of respective circuits in the cases wh~re MOSIC's for achieving the same circuit function are formed by the technique of this invention and by the Si gate MOS manufacturing technique of the prior art, respectively. By the adoption of the MOS matrix according to this invention, in comparison with the case of adopting the mere self-aligned type Si gate MOSROM, the ROM part which occupies a comparatively large area in the LSI is reduced by approximately 50~. As the result, it becomes possible to lessen the whole chip size by approximately 20%.
The operating speed of the ROM according to this invention will now be explained with reference to FIGs.
9(a) and 9(b). Since a ratioless circuit as shown in FIG.
9(b) is employed, the output level of the ROM has two states, and as previously set forth, the precharged data line holds the low level ox is shifted to the high level.
In this case, the operating speed of the ROM iS mainly i dependent upon the discharge time td in which the pre-charged data line is shifted to the high level. FIG. 9(a) illustrates th~ measurements of the relationship between the discharge time of the MOSROM shown in FIG. 9(b) ~the axis of ordinates, td) and the amplitude of the clock pulse supplied _ 9 _ .
: , - ;
Q : ~ :
to the gate of the load MOSFET of the enhancement mode (the axis of abscissas, Vcp), the MOSROM possessing 48 address lines and having 48enhancement or depletion MOSFET's con-nected in series. Herein, the output capacitance of the ROM
is made approximately 1.5 pF. As seen from the graph, the discharge time is smaller than 1.5 ~s. Especially as an IC
for an electronic desk top calculator, essehtially no pro-blem is posed in practical use because an operation in the order of 100 KHz is possible.
Description will now be mad~ of a method of manu-facturing the MOSROM according to this invention as shown in FIGs. 4(a) to 4(c) and FIG. 5, reference being had to FIGs.
6(a) to 6(f) and FIGs. 7(a) to 7(d). First, an Si02 film ' being about 1.4 ~ thick is formed in the surface of an N-type Si single crystal substrate 31 whose one principal surface is the (l 1 l)-face and which has a specific resistance of 5 to 8Qcm. Thereafter, those parts of the Si02 film on the principal surface of the substrate at which the MOSFET's are to be formed are removed in the shape of narrow slots. The exposed substrate surface is oxidized to form a thin Si02 film 30 (gate oxide film) of about 1,200 A there (refer to FIGs. 6(a) and 7(a)). Subsequently, boron ions are implanted into the substrate surface through the thin Si02 film 30 at a concentration of about 1.4 x 10ll k/cm2. Further, a photoresist material layer 50 is deposited onto that part of the thin oxide film 30 on the substrate surface at which the depletion MOSFET is not to be formed. Using the photoresist layer and the thick oxide film as a mask, boron ions are , . - ~
again implantad~ into the substrate surface through the exposed thin Si02 film at a concentration of 6.5 x 1011 k/cm2.
Thus, the P-type region 41 which constitutes the channel of ~ . ,; .
,.` . -- 10 --. . . , . - , . . .
1~798~;S
.
the D-MOSFET is formed (re~er to FIGs. 6(b) and 7(b)).
Subsequently, the photoresist layer is removed. Polycrys-tal silicon is deposited on the ~ntire oxide films to the extent of about 5,000 A. Those parts of the polycrystal Si layer which are other than parts for constructing the address lines (37, 38) are removed (refer to FIG. 6(c)).
Subsequently, using the parts 37 and 38 of the polycrystal Si layer left behind, the thin Si02 film 30 is removed to expose the substrate surface (refer to FIGs. 6(d) and 7(c)).
Subsequently, by employing the polycrystal Si layer 37, 38 : and the thick Si02 film 40 as a mask, boron is diffused into the exposed substrate surface by the conventional vapor dif-fusion process. Thus, the P+-type diffused regions 32, 33, 34, 47, 48 and 49 having a thickness of about 0.8 ~ are formed (refer to FIGs. 6(e) and 7(d)). Thereafter, the phosphosilicate glass (PSG film) 39 having a thickness of . about 0.9 to 1 ~ is deposited from vapor, to finish the MOSROM as shown in FIG. 6(f). In this way, there is produced the MOS matrix of the present invention as comprises the combination of the enhancement mode and depletion mode MOSFET's having the gate oxide films of substantially equal thicknesses. As described above, in the MOS matrix of this .
invention, the respective input lines of the polycrystal gi and the respective P+-type diffused layers intersect sub-stantially orthogonally, and all the insulating films under the polycrystal Si layers in any place of the intersection are made the equal thickness of about 1,200 A, so that the transistor operation is posItively carried out. Which : transistoxs are made the depletion type is determined by the 30 implantation of the boron ions as illustrated in FIG. 6~b).
Such technique of fabricating the depletion MOSFETIs is not .
-~9865 especially added, but in case of forming the circuit as shown in FIG. 5 or FIG. 9(b) within the surface of a single semiconductor substrate, the aforecited MOSFET's are fabri-cated by the same process as that of the other depletion MOSFET's, for example, the depletion load MOSFET's of the inverters.
To sum up, the ROM according to this invention has the following features:
(1) The ROM of this invention is constituted of the enhancement type and depletion type MOSFET's as the driving elements.
(2) The size of the ROM of this invention is remarkably small, and it is reduced by about 50%
as compared with that of the ROM of the prior-art Si gate stucture.
(3) The ROM of this invention is fabricated by a process which is compatible with the Si gate MOSLSI
employing the depletion loads as is presently being used extensively.
matrix as its input. A flip-flop circuit 21 consists of a plurality of stages (for example, k/2 stages) connected in - , .. .
iO79865 , cascade. Outputs from the respective stages are delivered directly or through inverter circuits 22 into the first MOS
matrix 23, whose outputs are delivered into the second MOS
matrix 24. The second MOS matrix provides outputs ~UT l to OUT n~ The matrices 23 and 24 have one MOSFET operative in the depletion or enhancement mode in any of the places in which input lines and output lines intersect. Such FET's are connected in series between a supply voltage VDD and a reference potehtial source (earth) at every column. Connected to the respective matrices as loads of the driving MOSFET's are enhancement mode MOSFET's (27, 28) which have clock signals applied to the gates thereof. In the figure, the driving MOSFET's with circles as indicated at 25 are those operating in the depletion mode, while the other driving MOSFET's are those operating in the enhancement mode. Each of the plurality of inverters 22 consists of a driving MOSFET
~' which operates in the enhancement mode, and a load MOSFET
which is connected in series therewith and which operates in the depletion mod~. As will be stated later, all the MOSFET's in the figure have gate insulating films (for ' example, Si02 films) of substantially equal thicknesses (about 500 to 1,500 angstroms) irrespective of the depletion mode or the enhancement mode. The depletion MOSFET's in the MOS
matrices are formed simultaneously with the depletion MOSFET's in the inverters 22 by quite an identical process.
The input lines of the first ahd second matrices are formed of polycrystal silicon wiri~ng layers, while the connection , from the output line of the first matrix to the input line of the secon~ matrix is performed by the use of an aluminum wiring wHich connects a P+-type diffused layer and the poly-crystal Si layer. When FIG. 5 is studied with reference to _ 7 : ~ . ' .
.. . . ...
1~798t;5 FIG. 3, the operation o~ the circuit in FIG. 5 Will be self-explanatory. To be particularly mentioned is that clock pulses ~1 and ~2 whose phases differ from each other are impressed on the gates of the load MOSFET's in the first and second matrices, respectively, and that the amplitudes of these pulses (for example, -12 to -16 volts) are greater than the amplitude of the supply volatge VDD (for example, -6 volts).
Referring now to FIGs. 4(a), 4(b) and 4(c), the ; device structure of the MOSROM according to this invention will be described. FIG. 4(a) is a plan view with a part of the MOSROM enlarged,while FIGs. 4(b) and 4(c) show X - X' and Y - Y' sections in FIG. 4(a), respectively. In the figures, numeral 31 designates an N-type single crystal Si substrate; numerals 32 to 34 and numerals 47 to 49 P+-type diffused layers which are formed by being self-aligned by Si gate electrodes; numerals 35, 36 and 43 gate insulating films of silicon dioxide which have essentially equal thick~
nesses (about 1,000 A); numerals 37 and 38 input lines of polycrystal Si, numeral 39 an insulating film of phosphosili-cate glass; numerals 41 and 42 P-type channel layers which are formed by implanting P-type impurity ions into selected areas of the surface of the substrate in order to form the depletion ~OSFET's;and numerals 44 to 46 field insulating films of silicon dioxide which are comparatively thick (about 1 to 2 ~). As apparent from the figures, one memory cell is formed in any of the places of in~ersection between the polycrystal Si wiring layers (37, 38) as the address input lines and the P -type diffused layers as the self-connected data output lines. The states of the respective memory cells are determined by the presence or absence of . .
107~865 .. .
the P-type channel formed by the ion implantation. All the memory cells have the thin gate oxide films so as to o~erate as the enhancement or depletion MOSFET.
As seen from the figures, the MOS matrix according to this invention has the self-aligned gate structure and needs n~ through-hole. It is there~ore understood that the ~ occupying area to the single bit is remarkably smaller in - the MOS matrix of this invention than in the prior-art one.
FIGs. 8(a) and 8(b) show by comparison the semiconductor chip sizes and the occupying areas of respective circuits in the cases wh~re MOSIC's for achieving the same circuit function are formed by the technique of this invention and by the Si gate MOS manufacturing technique of the prior art, respectively. By the adoption of the MOS matrix according to this invention, in comparison with the case of adopting the mere self-aligned type Si gate MOSROM, the ROM part which occupies a comparatively large area in the LSI is reduced by approximately 50~. As the result, it becomes possible to lessen the whole chip size by approximately 20%.
The operating speed of the ROM according to this invention will now be explained with reference to FIGs.
9(a) and 9(b). Since a ratioless circuit as shown in FIG.
9(b) is employed, the output level of the ROM has two states, and as previously set forth, the precharged data line holds the low level ox is shifted to the high level.
In this case, the operating speed of the ROM iS mainly i dependent upon the discharge time td in which the pre-charged data line is shifted to the high level. FIG. 9(a) illustrates th~ measurements of the relationship between the discharge time of the MOSROM shown in FIG. 9(b) ~the axis of ordinates, td) and the amplitude of the clock pulse supplied _ 9 _ .
: , - ;
Q : ~ :
to the gate of the load MOSFET of the enhancement mode (the axis of abscissas, Vcp), the MOSROM possessing 48 address lines and having 48enhancement or depletion MOSFET's con-nected in series. Herein, the output capacitance of the ROM
is made approximately 1.5 pF. As seen from the graph, the discharge time is smaller than 1.5 ~s. Especially as an IC
for an electronic desk top calculator, essehtially no pro-blem is posed in practical use because an operation in the order of 100 KHz is possible.
Description will now be mad~ of a method of manu-facturing the MOSROM according to this invention as shown in FIGs. 4(a) to 4(c) and FIG. 5, reference being had to FIGs.
6(a) to 6(f) and FIGs. 7(a) to 7(d). First, an Si02 film ' being about 1.4 ~ thick is formed in the surface of an N-type Si single crystal substrate 31 whose one principal surface is the (l 1 l)-face and which has a specific resistance of 5 to 8Qcm. Thereafter, those parts of the Si02 film on the principal surface of the substrate at which the MOSFET's are to be formed are removed in the shape of narrow slots. The exposed substrate surface is oxidized to form a thin Si02 film 30 (gate oxide film) of about 1,200 A there (refer to FIGs. 6(a) and 7(a)). Subsequently, boron ions are implanted into the substrate surface through the thin Si02 film 30 at a concentration of about 1.4 x 10ll k/cm2. Further, a photoresist material layer 50 is deposited onto that part of the thin oxide film 30 on the substrate surface at which the depletion MOSFET is not to be formed. Using the photoresist layer and the thick oxide film as a mask, boron ions are , . - ~
again implantad~ into the substrate surface through the exposed thin Si02 film at a concentration of 6.5 x 1011 k/cm2.
Thus, the P-type region 41 which constitutes the channel of ~ . ,; .
,.` . -- 10 --. . . , . - , . . .
1~798~;S
.
the D-MOSFET is formed (re~er to FIGs. 6(b) and 7(b)).
Subsequently, the photoresist layer is removed. Polycrys-tal silicon is deposited on the ~ntire oxide films to the extent of about 5,000 A. Those parts of the polycrystal Si layer which are other than parts for constructing the address lines (37, 38) are removed (refer to FIG. 6(c)).
Subsequently, using the parts 37 and 38 of the polycrystal Si layer left behind, the thin Si02 film 30 is removed to expose the substrate surface (refer to FIGs. 6(d) and 7(c)).
Subsequently, by employing the polycrystal Si layer 37, 38 : and the thick Si02 film 40 as a mask, boron is diffused into the exposed substrate surface by the conventional vapor dif-fusion process. Thus, the P+-type diffused regions 32, 33, 34, 47, 48 and 49 having a thickness of about 0.8 ~ are formed (refer to FIGs. 6(e) and 7(d)). Thereafter, the phosphosilicate glass (PSG film) 39 having a thickness of . about 0.9 to 1 ~ is deposited from vapor, to finish the MOSROM as shown in FIG. 6(f). In this way, there is produced the MOS matrix of the present invention as comprises the combination of the enhancement mode and depletion mode MOSFET's having the gate oxide films of substantially equal thicknesses. As described above, in the MOS matrix of this .
invention, the respective input lines of the polycrystal gi and the respective P+-type diffused layers intersect sub-stantially orthogonally, and all the insulating films under the polycrystal Si layers in any place of the intersection are made the equal thickness of about 1,200 A, so that the transistor operation is posItively carried out. Which : transistoxs are made the depletion type is determined by the 30 implantation of the boron ions as illustrated in FIG. 6~b).
Such technique of fabricating the depletion MOSFETIs is not .
-~9865 especially added, but in case of forming the circuit as shown in FIG. 5 or FIG. 9(b) within the surface of a single semiconductor substrate, the aforecited MOSFET's are fabri-cated by the same process as that of the other depletion MOSFET's, for example, the depletion load MOSFET's of the inverters.
To sum up, the ROM according to this invention has the following features:
(1) The ROM of this invention is constituted of the enhancement type and depletion type MOSFET's as the driving elements.
(2) The size of the ROM of this invention is remarkably small, and it is reduced by about 50%
as compared with that of the ROM of the prior-art Si gate stucture.
(3) The ROM of this invention is fabricated by a process which is compatible with the Si gate MOSLSI
employing the depletion loads as is presently being used extensively.
(4) The cascade ratioless circuit is applicable to the ROM of this in~ention, and LSI's with extra-ordinarily excellent characteristics can be realized by paying sufficient attention to the estimation of the operating speed.
The idea of this invention as stated above can also be applied to other complicated logical circuits such as a programmable logic array and a four-phase ratioless dynamic circuit. I~ is accordingly to be understood that the scope of right of the present application is not restricted to the foregoing specific aspects of performance.
~.
. -: . ,- ~ . ' ' , . '' ~- ' ' ,. :
The idea of this invention as stated above can also be applied to other complicated logical circuits such as a programmable logic array and a four-phase ratioless dynamic circuit. I~ is accordingly to be understood that the scope of right of the present application is not restricted to the foregoing specific aspects of performance.
~.
. -: . ,- ~ . ' ' , . '' ~- ' ' ,. :
Claims (11)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A semiconductor integrated circuit device comprising:
a semiconductor body having one conductivity type;
a plurality of first insulated gate field-effect tran-sistors each having a source, a drain and a gate and being arranged in and on said body in a matrix form in which said transistors are disposed along a plurality of rows and columns and the transistors in each row are connected in series;
a plurality of second insulated gate field-effect transistors each source electrode of which is connected in series wotj the drain of the first transistor connected at one end of each row and to each gate of which a first clock pulse is applied; and wherein the clock controlled second transistors are enhance-ment type and selected ones of the transistors in said matrix are depletion type and the gates of the transis-tors in each column of said matrix are formed of a common gate electrode layer.
a semiconductor body having one conductivity type;
a plurality of first insulated gate field-effect tran-sistors each having a source, a drain and a gate and being arranged in and on said body in a matrix form in which said transistors are disposed along a plurality of rows and columns and the transistors in each row are connected in series;
a plurality of second insulated gate field-effect transistors each source electrode of which is connected in series wotj the drain of the first transistor connected at one end of each row and to each gate of which a first clock pulse is applied; and wherein the clock controlled second transistors are enhance-ment type and selected ones of the transistors in said matrix are depletion type and the gates of the transis-tors in each column of said matrix are formed of a common gate electrode layer.
2. A semiconductor integrated circuit device according to claim 1, wherein for each row, the source of a field effect transistor in each column is contiguous with the drain of a field effect transistor in an adjacent column.
3. A semiconductor integrated circuit device according to claim 2, further comprising means for applying logic signals to selected ones of said common gate electrode layers; and a plurality of inverter circuits for applying the complements of said logic signals to the others of said common gate layers, each inverter circuit including a driving insulated gate field-effect transistor oper-ating in the enhancement mode and a load insulated gate field-effect transistor operating in the depletion mode and being connected in series with said driving transistor.
4. A semiconductor integrated circuit device according to claim 3, wherein some of said transistors in said matrix are depletion mode transistors so as to form a decoder.
5. A semiconductor integrated circuit device according to claim 4, wherein the source of the transistor connected at the other end of each row is connected to a ground terminal and the drains of the clock controlled transis-tors are connected to a power source terminal.
6. A semiconductor integrated circuit device according to claim 4, further comprising a read only memory matrix made up of a plurality of insulated gate field effect tran-sistors disposed in rows and columns, the transistors in each row being connected in series, and further including a multiplicity of enhancement mode insulated gate field-effect transistors the source electrode of each of which is connected in series with the drain of the transistor connected at one end of each row of said read only memory matrix, and to the gate electrode of each of which there is applied a second clock pulse, and wherein said read only memory matrix is connected in cascade with said decoder matrix.
7. A semiconductor integrated circuit device according to claim 6, wherein the source of the transistor con-nected at the other end of the row of each matrix is connected to a ground terminal and the drains of the transistors controlled by said first and second clock pulses are connected to a power source terminal.
8. A semiconductor integrated circuit device according to claim 1, further comprising a plurality of logical circuits, each including a driving insulated gate field-effect transistor and a load insulated gate field-effect transistor; and wherein said load transistors and selected ones of said transistors in said matrix are depletion type and said driving transistors and other transistors in said matrix are enhancement type.
9. A semiconductor integrated circuit device according to claim 8, wherein said load transistors of said logic circuits and said selected transistors in said matrix are depletion type transistors containing impurities deter-mining a conductivity type opposite to that of said semi-conductor body.
10. A semiconductor integrated circuit device according to claim 9, wherein for each row, the source of a field-effect transistor in each column is contiguous with the drain of a field-effect transistor in an adjacent column.
11. A semiconductor integrated circuit device according to claim 10, further comprising means for applying logic signals to said common gate electrode layers, wherein said logical circuits are constructed as inverter circuits for applying the complements of said logic signals to said common gate layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA327,604A CA1079865A (en) | 1975-09-04 | 1979-05-15 | Semiconductor integrated circuit device composed of insulated gate field-effect transistors |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50107350A JPS5851427B2 (en) | 1975-09-04 | 1975-09-04 | Manufacturing method of insulated gate type read-only memory |
| CA240,274A CA1070436A (en) | 1975-09-04 | 1975-11-24 | Semiconductor integrated circuit device composed of insulated gate field-effect transistors |
| CA327,604A CA1079865A (en) | 1975-09-04 | 1979-05-15 | Semiconductor integrated circuit device composed of insulated gate field-effect transistors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1079865A true CA1079865A (en) | 1980-06-17 |
Family
ID=27164213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA327,604A Expired CA1079865A (en) | 1975-09-04 | 1979-05-15 | Semiconductor integrated circuit device composed of insulated gate field-effect transistors |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1079865A (en) |
-
1979
- 1979-05-15 CA CA327,604A patent/CA1079865A/en not_active Expired
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1070436A (en) | Semiconductor integrated circuit device composed of insulated gate field-effect transistors | |
| US4130890A (en) | Integrated DDC memory with bitwise erase | |
| US7009243B2 (en) | Semiconductor memory device | |
| JP3900465B2 (en) | SOI field effect transistor | |
| US4672409A (en) | Nonvolatile semiconductor memory device | |
| US4122544A (en) | Electrically alterable floating gate semiconductor memory device with series enhancement transistor | |
| JP2000332132A (en) | Main body switch type soi(silicon-on-insulator) circuit and method of forming the same | |
| US4084108A (en) | Integrated circuit device | |
| KR100712089B1 (en) | Semiconductor Memory Device and Manufacturing Method thereof | |
| US4183093A (en) | Semiconductor integrated circuit device composed of insulated gate field-effect transistor | |
| KR20010070297A (en) | Erasable memory device and an associated method for erasing a memory cell therein | |
| GB2099649A (en) | Electrically programable read only memory | |
| EP0167595A4 (en) | An e?2 prom memory cell. | |
| EP0040377B1 (en) | Integrated circuit device for writing and reading information | |
| US4074238A (en) | Semiconductor read-only memory | |
| US4868628A (en) | CMOS RAM with merged bipolar transistor | |
| US4597000A (en) | Floating-gate memory cell | |
| US3875567A (en) | Memory circuit using variable threshold level field-effect device | |
| US4231055A (en) | Complementary MOS transistors without an isolation region | |
| CA1079865A (en) | Semiconductor integrated circuit device composed of insulated gate field-effect transistors | |
| US5252505A (en) | Method for manufacturing a semiconductor device | |
| US4636984A (en) | Semiconductor device having non-volatile storage transistors | |
| CA1079409A (en) | Semiconductor integrated circuit device composed of insulated gate field-effect transistors | |
| US5519244A (en) | Semiconductor device having aligned semiconductor regions and a plurality of MISFETs | |
| EP0022266B1 (en) | Semiconductor circuit device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |