JPS59186893U - cathode ray tube display device - Google Patents
cathode ray tube display deviceInfo
- Publication number
- JPS59186893U JPS59186893U JP8120283U JP8120283U JPS59186893U JP S59186893 U JPS59186893 U JP S59186893U JP 8120283 U JP8120283 U JP 8120283U JP 8120283 U JP8120283 U JP 8120283U JP S59186893 U JPS59186893 U JP S59186893U
- Authority
- JP
- Japan
- Prior art keywords
- erase
- display device
- ray tube
- cathode ray
- tube display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Digital Computer Display Output (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のイレーズ回路を備えた陰極線管ディスプ
レイ装置の表示用RAM周辺の回路図、第2図はそのイ
レーズ動作を示すフローチャート1、第3図は本考案の
一実施例に係るイレーズ回路を備えた陰極線管ディスプ
レイ装置の概略ブロック図、第4図はその画面データの
フォーマットを示す図、第5図はそのタイミングチャー
トである。
11・・・表示用RAM112・・・CRTコントロー
ラ、13・・・CRT、14・・・CPU、15.17
・・・バスコントローラ、16・・・イレーズレジスタ
、18・・・デーコーダ。FIG. 1 is a circuit diagram around a display RAM of a cathode ray tube display device equipped with a conventional erase circuit, FIG. 2 is a flowchart 1 showing the erase operation, and FIG. 3 is an erase circuit according to an embodiment of the present invention. FIG. 4 is a schematic block diagram of a cathode ray tube display device equipped with the same, FIG. 4 is a diagram showing the format of its screen data, and FIG. 5 is its timing chart. 11... Display RAM 112... CRT controller, 13... CRT, 14... CPU, 15.17
...Bus controller, 16.Erase register, 18.Decoder.
Claims (1)
スプレイ装置において、 イレーズ指令信号とイレーズデータをCPUに入力する
手段と、前記イレーズ指令信号がcpuに入力したとき
前記イレーズデータが書きこまれるイレーズレジスタと
、前記イレーズ指令信号カ入力したときデータ入力端子
がCPU側から前記イレーズレジスタ側に切り換わり前
記イレーズレジスタのイレーズデータを所定の時間、画
面表示用メモリに書きこむバスコントローラを設けたこ
とを特徴とする陰極線管ディスプレイ装置。[Claims for Utility Model Registration] In a cathode ray tube display device controlled by a microcomputer, there is provided a means for inputting an erase command signal and erase data to a CPU, and a means for inputting the erase data to the CPU when the erase command signal is input to the CPU. and a bus controller that switches the data input terminal from the CPU side to the erase register side when the erase command signal is input, and writes the erase data of the erase register to the screen display memory for a predetermined period of time. A cathode ray tube display device characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8120283U JPS59186893U (en) | 1983-05-31 | 1983-05-31 | cathode ray tube display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8120283U JPS59186893U (en) | 1983-05-31 | 1983-05-31 | cathode ray tube display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59186893U true JPS59186893U (en) | 1984-12-11 |
Family
ID=30211170
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8120283U Pending JPS59186893U (en) | 1983-05-31 | 1983-05-31 | cathode ray tube display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59186893U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5468121A (en) * | 1977-11-11 | 1979-06-01 | Hitachi Ltd | Display unit |
-
1983
- 1983-05-31 JP JP8120283U patent/JPS59186893U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5468121A (en) * | 1977-11-11 | 1979-06-01 | Hitachi Ltd | Display unit |
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