JPS59115385U - schedule controller - Google Patents
schedule controllerInfo
- Publication number
- JPS59115385U JPS59115385U JP798783U JP798783U JPS59115385U JP S59115385 U JPS59115385 U JP S59115385U JP 798783 U JP798783 U JP 798783U JP 798783 U JP798783 U JP 798783U JP S59115385 U JPS59115385 U JP S59115385U
- Authority
- JP
- Japan
- Prior art keywords
- schedule controller
- running signal
- controlled device
- input terminal
- schedule
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Clocks (AREA)
- Audible And Visible Signals (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例の外観を示す正面図、第２図
は本考案の一実施例の機能ブロックを示すブロック図、
第３図は本考案の一実施例による連動機器の接続を示す
ブロック図である。
１・・・・・・ケース、２・・・・・・表示面、８・・
・陰極線管、１０・・・設定制御手段、１１・・・・・
・表示制御手段、１５・・・・・・設定プログラムメモ
リ、１７・・・・・・カレンダ一時計、１９・・・・・
・出力制御手段、３１・・・・・・スケジュールコント
ローラ、３２・・・・・・被制御機器、３３・・・・・
・連動機器、ｔ５・・・・・・運転中信号入力端子、ｔ
６・・・・・・制御出力端子、ｔ７・・・・・・外部出
力。FIG. 1 is a front view showing the appearance of an embodiment of the present invention, and FIG. 2 is a block diagram showing functional blocks of an embodiment of the present invention.
FIG. 3 is a block diagram showing the connection of interlocking devices according to an embodiment of the present invention. 1...Case, 2...Display surface, 8...
- Cathode ray tube, 10... Setting control means, 11...
・Display control means, 15... Setting program memory, 17... Calendar clock, 19...
- Output control means, 31... Schedule controller, 32... Controlled equipment, 33...
・Interlocking equipment, t5...During signal input terminal, t
6...Control output terminal, t7...External output.
Claims (1)
オンオフ制御するスケジュールコントローラにおいて、
被制御機器からの運転中信号が入力する運転中信号入力
端子と、該運転中信号入力端子に接続され、運転中信号
を外部に出力する外部出力端子とを設けたことを特徴と
するスケジュールコントローラ。In a schedule controller that controls on/off of a controlled device according to a preset time schedule,
A schedule controller comprising: a running signal input terminal into which a running signal from a controlled device is input; and an external output terminal connected to the running signal input terminal and outputting the running signal to the outside. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP798783U JPS59115385U (en) | 1983-01-25 | 1983-01-25 | schedule controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP798783U JPS59115385U (en) | 1983-01-25 | 1983-01-25 | schedule controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59115385U true JPS59115385U (en) | 1984-08-03 |
Family
ID=30139499
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP798783U Pending JPS59115385U (en) | 1983-01-25 | 1983-01-25 | schedule controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59115385U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54155382A (en) * | 1978-05-30 | 1979-12-07 | Rhythm Watch Co | Program timer |
-
1983
- 1983-01-25 JP JP798783U patent/JPS59115385U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54155382A (en) * | 1978-05-30 | 1979-12-07 | Rhythm Watch Co | Program timer |
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