JPS5836392U - Week programmer - Google Patents
Week programmerInfo
- Publication number
- JPS5836392U JPS5836392U JP13007481U JP13007481U JPS5836392U JP S5836392 U JPS5836392 U JP S5836392U JP 13007481 U JP13007481 U JP 13007481U JP 13007481 U JP13007481 U JP 13007481U JP S5836392 U JPS5836392 U JP S5836392U
- Authority
- JP
- Japan
- Prior art keywords
- week
- programmer
- day
- time
- program
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Clocks (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図ないし第５図は従来例を説明するための図であり
、第１図および第２図は構成を示すブロック図、第３図
および第４図はプログラム設定を示す図、第５図は従来
例の表示器６の前面図である。第６図はこの考案の実施
例の構成を示すブロック図である。第７図および第８図
はこの実施例の作用説明図である。
２・・・・・・入カキ−１３・・・・・・時計回路、５
・・・・・・出力回路、６・・・・・・表示器、２１・
・・・・・メモリ、２２・・・・・・制御回路、２３・
・・・・・読み出し回路、２４・・・・・・切換スイッ
チ。1 to 5 are diagrams for explaining the conventional example, FIGS. 1 and 2 are block diagrams showing the configuration, FIGS. 3 and 4 are diagrams showing program settings, and FIG. 1 is a front view of a conventional display device 6. FIG. FIG. 6 is a block diagram showing the configuration of an embodiment of this invention. FIGS. 7 and 8 are explanatory diagrams of the operation of this embodiment. 2...Input key-13...Clock circuit, 5
...Output circuit, 6...Display device, 21.
...Memory, 22...Control circuit, 23.
...readout circuit, 24...changeover switch.
Claims (1)
刻カウンターと、上記入カキ−によって出力Ａ６、曜日
、時刻等を指定することにより出力扁毎に曜日、時刻等
からなるプログラムを書き込み、または読み出しが行え
るプロゲララメモリ−と、上記プログラムの書き込みま
たはその読み出しの時その内容を表示する人足器とを備
えた・クイークプログラマーにおいて、上記プログラム
メモリーが複数個のプログラムモードを記憶するメモリ
ーエリアを有するとともに、入カキ−とは別に上記複数
個のプログラムモードを選択的に切り換えるスイッチを
設シコたことを特徴とするウィークプログラマ−０By specifying the output A6, day of the week, time, etc. using the input key, the day/time counter that stores the current day of the week or time, and the input key, a program consisting of the day of the week, time, etc. is written for each output plane, Or, in a quick programmer, the program memory is a memory that stores a plurality of program modes. A weak programmer-0 characterized in that it has a switch area and a switch for selectively switching between the plurality of program modes, in addition to the input key.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13007481U JPS5836392U (en) | 1981-09-01 | 1981-09-01 | Week programmer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13007481U JPS5836392U (en) | 1981-09-01 | 1981-09-01 | Week programmer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5836392U true JPS5836392U (en) | 1983-03-09 |
Family
ID=29923725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13007481U Pending JPS5836392U (en) | 1981-09-01 | 1981-09-01 | Week programmer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5836392U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5170427A (en) * | 1974-12-15 | 1976-06-18 | Matsushita Electric Works Ltd | |
| JPS55107987A (en) * | 1979-02-14 | 1980-08-19 | Toshiba Corp | Electronic time limiter |
-
1981
- 1981-09-01 JP JP13007481U patent/JPS5836392U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5170427A (en) * | 1974-12-15 | 1976-06-18 | Matsushita Electric Works Ltd | |
| JPS55107987A (en) * | 1979-02-14 | 1980-08-19 | Toshiba Corp | Electronic time limiter |
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