JPS59115386U - schedule controller - Google Patents
schedule controllerInfo
- Publication number
- JPS59115386U JPS59115386U JP798883U JP798883U JPS59115386U JP S59115386 U JPS59115386 U JP S59115386U JP 798883 U JP798883 U JP 798883U JP 798883 U JP798883 U JP 798883U JP S59115386 U JPS59115386 U JP S59115386U
- Authority
- JP
- Japan
- Prior art keywords
- control
- schedule controller
- output signal
- control output
- controlled device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Feedback Control In General (AREA)
- Electric Clocks (AREA)
- Audible And Visible Signals (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案の一実施例の外観を示す正面図、第2図
は本考案の一実施例の機能ブロックを示すブロック図、
第3図は本考案の一実施例における使用例を示すブ町ツ
ク図である。
1・・・・・・ケース、2・・・・・・表示面、8・・
・・・・陰極線管、10・・・・・・設定制御手段、1
1・・・・・・表示制御手段、15・・・・・・設定プ
ログラムメモリ、17・・・・・・カレンダ一時計、1
9・・・・・・出力制御手段、20・・・・・・アンド
ゲート、31・・・・・・スケジュールコントローラ、
32・・・・・・照明灯、33・・・・・・照度センサ
、t6・・・・・・制御出力端子、t7・・・・・・外
部制御信号入力端子。FIG. 1 is a front view showing the appearance of an embodiment of the present invention, and FIG. 2 is a block diagram showing functional blocks of an embodiment of the present invention.
FIG. 3 is a block diagram showing an example of use in one embodiment of the present invention. 1...Case, 2...Display surface, 8...
... Cathode ray tube, 10 ... Setting control means, 1
1... Display control means, 15... Setting program memory, 17... Calendar clock, 1
9... Output control means, 20... AND gate, 31... Schedule controller,
32...Lighting lamp, 33...Illuminance sensor, t6...Control output terminal, t7...External control signal input terminal.
Claims (1)
対するオン又はオフの制御出力信号を発生する出力制御
手段を備えたスケジュールコントローラにおいて、外部
制御信号入力端子に入力する外部制御信号に応じて、前
記出力制御手段の制御出力信号を強制的にオフ又はオン
の制御出力信号に変換する強制手段を設けたことを特徴
とするスケジュールコントローラ。In a schedule controller comprising an output control means for generating an ON or OFF control output signal for a controlled device according to a preset time schedule, the output control means is configured to generate an ON or OFF control output signal for a controlled device according to an external control signal input to an external control signal input terminal. 1. A schedule controller comprising a forcing means for forcibly converting a control output signal into an OFF or ON control output signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP798883U JPS59115386U (en) | 1983-01-25 | 1983-01-25 | schedule controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP798883U JPS59115386U (en) | 1983-01-25 | 1983-01-25 | schedule controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59115386U true JPS59115386U (en) | 1984-08-03 |
Family
ID=30139500
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP798883U Pending JPS59115386U (en) | 1983-01-25 | 1983-01-25 | schedule controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59115386U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51102455A (en) * | 1975-03-05 | 1976-09-09 | Funai Electric Co | DENSHITAIMA SOCHI |
-
1983
- 1983-01-25 JP JP798883U patent/JPS59115386U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51102455A (en) * | 1975-03-05 | 1976-09-09 | Funai Electric Co | DENSHITAIMA SOCHI |
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