JPS59115386U

JPS59115386U - schedule controller

Info

Publication number: JPS59115386U
Application number: JP798883U
Authority: JP
Inventors: 中野　浩三; 西川　喜一; 瀬田　達夫; 佐藤　寿也; 隆宮田; 南山　茂利
Original assignee: 株式会社建築設備設計研究所; 大崎電気工業株式会社
Priority date: 1983-01-25
Filing date: 1983-01-25
Publication date: 1984-08-03

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は本考案の一実施例の外観を示す正面図、第２図
は本考案の一実施例の機能ブロックを示すブロック図、
第３図は本考案の一実施例における使用例を示すブ町ツ
ク図である。１・・・・・・ケース、２・・・・・・表示面、８・・
・・・・陰極線管、１０・・・・・・設定制御手段、１
１・・・・・・表示制御手段、１５・・・・・・設定プ
ログラムメモリ、１７・・・・・・カレンダ一時計、１
９・・・・・・出力制御手段、２０・・・・・・アンド
ゲート、３１・・・・・・スケジュールコントローラ、
３２・・・・・・照明灯、３３・・・・・・照度センサ
、ｔ６・・・・・・制御出力端子、ｔ７・・・・・・外
部制御信号入力端子。FIG. 1 is a front view showing the appearance of an embodiment of the present invention, and FIG. 2 is a block diagram showing functional blocks of an embodiment of the present invention.
FIG. 3 is a block diagram showing an example of use in one embodiment of the present invention. 1...Case, 2...Display surface, 8...
... Cathode ray tube, 10 ... Setting control means, 1
1... Display control means, 15... Setting program memory, 17... Calendar clock, 1
9... Output control means, 20... AND gate, 31... Schedule controller,
32...Lighting lamp, 33...Illuminance sensor, t6...Control output terminal, t7...External control signal input terminal.

Claims

[Scope of utility model registration request]

In a schedule controller comprising an output control means for generating an ON or OFF control output signal for a controlled device according to a preset time schedule, the output control means is configured to generate an ON or OFF control output signal for a controlled device according to an external control signal input to an external control signal input terminal. 1. A schedule controller comprising a forcing means for forcibly converting a control output signal into an OFF or ON control output signal.